427e5f18e8
reason: 1 We place interrupt handling functions of the same priority into the work queue corresponding to that priority, allowing high-priority interrupts to preempt low-priority ones, thus ensuring the real-time performance of high-priority interrupts. 2 The sole purpose of the interrupt handler is to wake up the work queue of the corresponding priority and execute the interrupt handling function. 3 Compared to the functionality of isr threads, this approach saves more memory, particularly when the number of interrupts is large. Signed-off-by: hujun5 <hujun5@xiaomi.com>
44 lines
1.4 KiB
CMake
44 lines
1.4 KiB
CMake
# ##############################################################################
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# sched/irq/CMakeLists.txt
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. The ASF licenses this
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# file to you under the Apache License, Version 2.0 (the "License"); you may not
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# use this file except in compliance with the License. You may obtain a copy of
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# the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations under
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# the License.
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#
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# ##############################################################################
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set(SRCS irq_initialize.c irq_attach.c irq_attach_thread.c irq_attach_wqueue.c
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irq_dispatch.c irq_unexpectedisr.c)
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if(CONFIG_SPINLOCK)
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list(APPEND SRCS irq_spinlock.c)
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endif()
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if(CONFIG_IRQCOUNT)
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list(APPEND SRCS irq_csection.c)
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endif()
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if(CONFIG_SCHED_IRQMONITOR)
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list(APPEND SRCS irq_foreach.c)
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if(CONFIG_FS_PROCFS)
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list(APPEND SRCS irq_procfs.c)
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endif()
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endif()
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if(CONFIG_IRQCHAIN)
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list(APPEND SRCS irq_chain.c)
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endif()
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target_sources(sched PRIVATE ${SRCS})
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