709 lines
18 KiB
C
709 lines
18 KiB
C
/****************************************************************************
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* arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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* Daniel Pereira Volpato <dpo@certi.org.br>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING INANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "stm32_pwr.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become
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* ready. that is a very long delay, but if the clock does not become
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* ready we are hosed anyway. Normally this is very fast, but I have
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* seen at least one board that required this long, long timeout for
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* the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/* HSE divisor to yield ~1MHz RTC clock (valid for HSE = 8MHz) */
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#define HSE_DIVISOR RCC_CR_RTCPRE_HSEd8
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rcc_reset
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*
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* Description:
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* Put all RCC registers in reset state
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*
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****************************************************************************/
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static inline void rcc_reset(void)
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{
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uint32_t regval;
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/* Reset CFGR register */
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putreg32(RCC_CFGR_RESET, STM32_RCC_CFGR);
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/* Reset CR register */
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putreg32(RCC_CR_RESET, STM32_RCC_CR);
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/* Reset PLLCFGR register */
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putreg32(RCC_PLLCFGR_RESET, STM32_RCC_PLLCFG);
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/* DBG clock enable */
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regval = RCC_APB1ENR_DBGEN;
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putreg32(regval, STM32_RCC_APB1ENR);
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}
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/****************************************************************************
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* Name: rcc_enableio
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*
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* Description:
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* Enable selected GPIO
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*
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****************************************************************************/
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static inline void rcc_enableio(void)
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{
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uint32_t regval = 0;
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/* REVISIT: */
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regval |= (RCC_IOPENR_IOPAEN | RCC_IOPENR_IOPBEN | RCC_IOPENR_IOPCEN | \
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RCC_IOPENR_IOPDEN | RCC_IOPENR_IOPFEN);
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putreg32(regval, STM32_RCC_IOPENR); /* Enable GPIO */
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}
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/****************************************************************************
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* Name: rcc_enableahb
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*
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* Description:
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* Enable selected AHB peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb(void)
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{
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uint32_t regval = 0;
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/* Set the appropriate bits in the AHBENR register to enabled the
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* selected AHBENR peripherals.
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*/
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regval = getreg32(STM32_RCC_AHBENR);
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#ifdef CONFIG_STM32F0L0G0_DMA1
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/* DMA 1 clock enable */
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regval |= RCC_AHBENR_DMA1EN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_MIF
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/* Memory interface clock enable */
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regval |= RCC_AHBENR_MIFEN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_CRC
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/* CRC clock enable */
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regval |= RCC_AHBENR_CRCEN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_RNG
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/* Random number generator clock enable */
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regval |= RCC_AHBENR_RNGEN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_AES
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/* AES modules clock enable */
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regval |= RCC_AHBENR_AESEN;
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#endif
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putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableapb1
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*
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* Description:
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* Enable selected APB1 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb1(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB1ENR register to enabled the
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* selected APB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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#ifdef CONFIG_STM32F0L0G0_TIM2
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/* Timer 2 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_TIM2EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM3
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/* Timer 3 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_TIM3EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM6
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/* Timer 6 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_TIM6EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM7
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/* Timer 7 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_TIM7EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_SPI2
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/* SPI 2 clock enable */
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regval |= RCC_APB1ENR_SPI2EN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_USART2
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/* USART 2 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_USART2EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_USART3
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/* USART 3 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_USART3EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_USART4
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/* USART 4 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_USART4EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_LPUSART1
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/* USART 5 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_LPUSART1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_I2C1
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/* I2C 1 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_I2C1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_I2C2
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/* I2C 2 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB1ENR_I2C2EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_PWR
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/* Power interface clock enable */
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regval |= RCC_APB1ENR_PWREN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_DAC1
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/* DAC 1 interface clock enable */
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regval |= RCC_APB1ENR_DAC1EN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_LPTIM1
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/* LPTIM1 clock enable */
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regval |= RCC_APB1ENR_LPTIM1EN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_LPTIM2
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/* LPTIM2 clock enable */
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regval |= RCC_APB1ENR_LPTIM2EN;
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#endif
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putreg32(regval, STM32_RCC_APB1ENR);
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}
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/****************************************************************************
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* Name: rcc_enableapb2
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*
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* Description:
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* Enable selected APB2 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb2(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB2ENR register to enabled the
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* selected APB2 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB2ENR);
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#ifdef CONFIG_STM32F0L0G0_SYSCFG
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/* SYSCFG clock */
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regval |= RCC_APB2ENR_SYSCFGEN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM1
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/* TIM1 Timer clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB2ENR_TIM1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_SPI1
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/* SPI 1 clock enable */
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regval |= RCC_APB2ENR_SPI1EN;
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#endif
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#ifdef CONFIG_STM32F0L0G0_USART1
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/* USART1 clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB2ENR_USART1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM14
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/* TIM14 Timer clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB2ENR_TIM14EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM15
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/* TIM5 Timer clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB2ENR_TIM15EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM16
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/* TIM16 Timer clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB2ENR_TIM16EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_TIM17
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/* TIM17 Timer clock enable */
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#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
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regval |= RCC_APB2ENR_TIM17EN;
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#endif
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#endif
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#ifdef CONFIG_STM32F0L0G0_ADC1
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/* ADC 1 clock enable */
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regval |= RCC_APB2ENR_ADC1EN;
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#endif
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putreg32(regval, STM32_RCC_APB2ENR);
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}
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/****************************************************************************
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* Name: stm32_rcc_enablehse
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*
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* Description:
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* Enable the External High-Speed (HSE) Oscillator.
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*
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****************************************************************************/
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#if (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
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static inline bool stm32_rcc_enablehse(void)
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{
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uint32_t regval;
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volatile int32_t timeout;
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */
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regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */
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#else
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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#endif
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the HSERDY flag is set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
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{
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/* If so, then return TRUE */
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return true;
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}
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}
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/* In the case of a timeout starting the HSE, we really don't have a
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* strategy. This is almost always a hardware failure or misconfiguration.
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*/
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return false;
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}
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#endif
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/****************************************************************************
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* Name: stm32_stdclockconfig
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*
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* Description:
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* Called to change to new clock based on settings in board.h.
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes or any clocking other than PLL driven by the HSE.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
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static void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
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uint16_t pwrcr;
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#endif
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#ifdef CONFIG_STM32F0L0G0_PWR
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uint32_t pwr_vos;
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#endif
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uint32_t flash_ws;
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/* Enable PWR clock from APB1 to give access to PWR_CR register */
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regval = getreg32(STM32_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32_RCC_APB1ENR);
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/* Two voltage ranges are available:
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*
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* Range 1: High-performance range (default)
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* Typical output voltage 1.2 V
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* SYSLCK up to 64 MHz
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*
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* Range 2: Low-power range
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* Typical output voltage 1.0V
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* SYSLCK up to 16 MHz
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*
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* Flash wait states (latency) according to range and HCLK:
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*
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* Range 1:
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* - Flash 0WS if HCLK <= 24
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* - Flash 1WS if HCLK <= 48
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* - Flash 2WS if HCLK <= 64
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*
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* Range 2:
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* - Flash 0WS if HCLK <= 8
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* - Flash 1WS if HCLK <= 16
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*
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* Where HCLK = (SYSCLK / HPRE div)
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*/
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if (STM32_SYSCLK_FREQUENCY > 16000000)
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{
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#ifdef CONFIG_STM32F0L0G0_PWR
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pwr_vos = PWR_CR1_VOS_RANGE1;
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#endif
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if (STM32_HCLK_FREQUENCY <= 24000000)
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{
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flash_ws = FLASH_ACR_LATENCY_0;
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}
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else if (STM32_HCLK_FREQUENCY <= 48000000)
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{
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flash_ws = FLASH_ACR_LATENCY_1;
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}
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else
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{
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flash_ws = FLASH_ACR_LATENCY_2;
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}
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}
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else
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{
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#ifdef CONFIG_STM32F0L0G0_PWR
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pwr_vos = PWR_CR1_VOS_RANGE2;
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#endif
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if (STM32_HCLK_FREQUENCY <= 8000000)
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{
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flash_ws = FLASH_ACR_LATENCY_0;
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}
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else
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{
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flash_ws = FLASH_ACR_LATENCY_1;
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}
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}
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#ifdef CONFIG_STM32F0L0G0_PWR
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stm32_pwr_setvos(pwr_vos);
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#endif
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#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
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/* If RTC / LCD selects HSE as clock source, the RTC prescaler
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* needs to be set before HSEON bit is set.
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*/
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/* The RTC domain has write access denied after reset,
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* you have to enable write access using DBP bit in the PWR CR
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* register before to selecting the clock source ( and the PWR
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* peripheral must be enabled)
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32_RCC_APB1ENR);
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pwrcr = getreg16(STM32_PWR_CR);
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putreg16(pwrcr | PWR_CR_DBP, STM32_PWR_CR);
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/* Set the RTC clock divisor */
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regval = getreg32(STM32_RCC_CSR);
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regval &= ~RCC_CSR_RTCSEL_MASK;
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regval |= RCC_CSR_RTCSEL_HSE;
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putreg32(regval, STM32_RCC_CSR);
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_RTCPRE_MASK;
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regval |= HSE_DIVISOR;
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putreg32(regval, STM32_RCC_CR);
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|
|
/* Restore the previous state of the DBP bit */
|
|
|
|
putreg32(regval, STM32_PWR_CR);
|
|
|
|
#endif
|
|
|
|
/* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
|
|
|
|
#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
|
|
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE))
|
|
|
|
/* The PLL is using the HSE, or the HSE is the system clock. In either
|
|
* case, we need to enable HSE clocking.
|
|
*/
|
|
|
|
if (!stm32_rcc_enablehse())
|
|
{
|
|
/* In the case of a timeout starting the HSE, we really don't have a
|
|
* strategy. This is almost always a hardware failure or
|
|
* misconfiguration (for example, if no crystal is fitted on the board.
|
|
*/
|
|
|
|
return;
|
|
}
|
|
|
|
#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
|
|
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSI)
|
|
|
|
/* The PLL is using the HSI, or the HSI is the system clock. In either
|
|
* case, we need to enable HSI clocking.
|
|
*/
|
|
|
|
regval = getreg32(STM32_RCC_CR); /* Enable the HSI */
|
|
regval |= RCC_CR_HSION;
|
|
putreg32(regval, STM32_RCC_CR);
|
|
|
|
/* Wait until the HSI clock is ready. Since this is an internal clock, no
|
|
* timeout is expected
|
|
*/
|
|
|
|
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0);
|
|
|
|
#endif
|
|
|
|
/* Configure FLASH wait states and enable prefetch */
|
|
|
|
regval = getreg32(STM32_FLASH_ACR);
|
|
regval &= ~FLASH_ACR_LATENCY_MASK;
|
|
regval |= (flash_ws & FLASH_ACR_LATENCY_MASK) | FLASH_ACR_PRFTEN;
|
|
putreg32(regval, STM32_FLASH_ACR);
|
|
|
|
/* Set the HCLK source/divider */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_HPRE_MASK;
|
|
regval |= STM32_RCC_CFGR_HPRE;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
/* Set the PCLK1 divider */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_PPRE1_MASK;
|
|
regval |= STM32_RCC_CFGR_PPRE1;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
/* If we are using the PLL, configure and start it */
|
|
|
|
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
|
|
|
|
/* Configure PLLs */
|
|
|
|
regval = STM32_PLLCFG_PLLSRC | STM32_PLLCFG_PLLCFG;
|
|
|
|
/* Configure PLL clock input */
|
|
|
|
regval |= STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN;
|
|
|
|
/* Configure PLL clock outputs division */
|
|
|
|
#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
|
|
defined(CONFIG_ARCH_CHIP_STM32G070RB)
|
|
regval |= STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLR;
|
|
#else
|
|
regval |= STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR;
|
|
#endif
|
|
|
|
/* Write PLLCFG register */
|
|
|
|
putreg32(regval, STM32_RCC_PLLCFG);
|
|
|
|
/* Enable PLL */
|
|
|
|
regval = getreg32(STM32_RCC_CR);
|
|
regval |= RCC_CR_PLLON;
|
|
putreg32(regval, STM32_RCC_CR);
|
|
#endif
|
|
|
|
/* Select the system clock source (probably the PLL) */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_SW_MASK;
|
|
regval |= STM32_SYSCLK_SW;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
/* Wait until the selected source is used as the system clock source */
|
|
|
|
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
|
|
|
|
#if defined(CONFIG_STM32F0L0G0_IWDG) || \
|
|
defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
|
|
/* Low speed internal clock source LSI
|
|
*
|
|
* TODO: There is another case where the LSI needs to
|
|
* be enabled: if the MCO pin selects LSI as source.
|
|
*/
|
|
|
|
stm32_rcc_enablelsi();
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
|
|
/* Low speed external clock source LSE
|
|
*
|
|
* TODO: There is another case where the LSE needs to
|
|
* be enabled: if the MCO pin selects LSE as source.
|
|
*
|
|
* TODO: There is another case where the LSE needs to
|
|
* be enabled: if TIM9-10 Channel 1 selects LSE as input.
|
|
*
|
|
* TODO: There is another case where the LSE needs to
|
|
* be enabled: if TIM10-11 selects LSE as ETR Input.
|
|
*
|
|
*/
|
|
|
|
stm32_rcc_enablelse();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: rcc_enableperiphals
|
|
****************************************************************************/
|
|
|
|
static inline void rcc_enableperipherals(void)
|
|
{
|
|
rcc_enableio();
|
|
rcc_enableahb();
|
|
rcc_enableapb2();
|
|
rcc_enableapb1();
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|