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arm_addrenv.c
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Add a configuration option for dynamic stack management
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2014-09-13 12:25:32 -06:00 |
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arm_allocpage.c
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More trailing whilespace removal
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2014-04-13 16:22:22 -06:00 |
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arm_assert.c
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Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h
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2014-08-08 17:53:55 -06:00 |
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arm_blocktask.c
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ARM: Move address environment switch from the task switchers to the interrupt handler. That may save doing the actin multiple times per interrupt
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2014-08-28 06:34:09 -06:00 |
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arm_checkmapping.c
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Improve Cortex-A5 context switching so that a little less copying is done
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2013-07-24 07:47:51 -06:00 |
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arm_coherent_dcache.c
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up_coherent_dcache should do nothing the the length is zero
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2014-08-26 14:51:53 -06:00 |
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arm_copyarmstate.c
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Trivial kernel build related fixes for consistency
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2014-09-11 12:35:23 -06:00 |
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arm_copyfullstate.c
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Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures
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2014-08-08 18:39:28 -06:00 |
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arm_dataabort.c
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Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h
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2014-08-08 17:53:55 -06:00 |
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arm_doirq.c
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Fix an error introduced into ALL implmentations of interrupt dispatch logic
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2014-08-28 08:41:57 -06:00 |
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arm_elf.c
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ELF relocations. Some relocation types do not have a named symbol associated with them. The design did not account for that case
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2014-09-09 16:52:51 -06:00 |
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arm_fpuconfig.S
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Cosmetic spaces to tabs change
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2013-12-08 10:38:33 -06:00 |
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arm_fullcontextrestore.S
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Comsetic updates to comments, debug output
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2014-09-12 10:31:58 -06:00 |
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arm_head.S
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Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling
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2014-06-21 09:55:09 -06:00 |
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arm_initialstate.c
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All tasks, even user mode tasks, must start in supervisor mode until they get past the start-up trampoline
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2014-09-11 18:42:52 -06:00 |
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arm_l2cc_pl310.c
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ARM: Move L2 cache initialization to much later in the sequence
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2014-07-27 10:03:33 -06:00 |
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arm_memcpy.S
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Ooops... last (cosmetic) changes were still in the editor
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2014-05-06 15:00:39 -06:00 |
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arm_mmu.c
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Misc changed to get the SAMA5 ELF configuration with address environments working
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2014-08-25 13:28:13 -06:00 |
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arm_pgalloc.c
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Add configuration to use the fixed DRAM mapping for the page pool (if available) instead of remapping dynamically to access L2 page tables and page data. Also, add logic in address environment creation to initialize the shared data at the beginning of the .bss/.data process memory region.
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2014-09-10 08:41:01 -06:00 |
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arm_pghead.S
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Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling
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2014-06-21 09:55:09 -06:00 |
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arm_pginitialize.c
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More ARMv7-A files that are just copies of the ARMv4/5 files for now
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2013-07-19 11:43:04 -06:00 |
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arm_prefetchabort.c
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Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h
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2014-08-08 17:53:55 -06:00 |
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arm_releasepending.c
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Add address environment support to ALL implementatins of up_release_pending()
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2014-08-28 08:10:19 -06:00 |
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arm_reprioritizertr.c
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Add address environment support to ALL implementatins of up_reprioritize_rtr()
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2014-08-28 07:54:07 -06:00 |
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arm_restorefpu.S
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ARMv7-N: Fix a copy error introduced in the previous check-in
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2013-07-23 19:09:17 -06:00 |
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arm_savefpu.S
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ARMv7-N: Fix a copy error introduced in the previous check-in
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2013-07-23 19:09:17 -06:00 |
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arm_saveusercontext.S
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Add a hello world configuration to help with the SAMA5 bringup
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2013-07-26 15:28:01 -06:00 |
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arm_schedulesigaction.c
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Mostly cosmetic changes
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2014-09-04 10:28:38 -06:00 |
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arm_sigdeliver.c
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Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h
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2014-08-08 17:53:55 -06:00 |
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arm_syscall.c
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ARMv7-A: Modify up_fullcontextrestore() for CONFIG_BUILD_KERNEL. It changed CPSR while in kernel. That will crash is the new CPSR is user mode while executing in kernel space. Fixed by adding a SYS_context_restore system call. There is an alternative, simpler modification to up_fullcontextrestore() that could have been done: It might have been possible to use the SPSR instead of the CPRSR and then do an exception return from up_fullcontextrestore(). That would be more efficient, but I never tried it.
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2014-09-12 08:04:27 -06:00 |
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arm_unblocktask.c
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ARM: Move address environment switch from the task switchers to the interrupt handler. That may save doing the actin multiple times per interrupt
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2014-08-28 06:34:09 -06:00 |
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arm_undefinedinsn.c
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Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures
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2014-08-08 18:39:28 -06:00 |
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arm_va2pte.c
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Improve Cortex-A5 context switching so that a little less copying is done
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2013-07-24 07:47:51 -06:00 |
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arm_vectoraddrexcptn.S
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Fix all occurrences of "the the" in documentation and comments
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2013-08-27 09:40:19 -06:00 |
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arm_vectors.S
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Fix logic for returning from exceptions to user-mode contexts
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2014-09-11 18:43:30 -06:00 |
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arm_vectortab.S
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SVC is the preferred mnemonic vs. SWI for cortex A
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2014-01-05 16:21:41 -06:00 |
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arm_vfork.S
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More trailing whilespace removal
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2014-04-13 16:22:22 -06:00 |
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arm.h
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Add support for .data and .bss in SDRAM
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2014-01-28 14:35:03 -06:00 |
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cache.h
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ARM: Move L2 cache initialization to much later in the sequence
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2014-07-27 10:03:33 -06:00 |
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cp15_cacheops.h
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Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place.
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2014-07-26 16:54:19 -06:00 |
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cp15_clean_dcache.S
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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cp15_coherent_dcache.S
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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cp15_flush_dcache.S
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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cp15_invalidate_dcache_all.S
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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cp15_invalidate_dcache.S
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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cp15.h
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Trivial updates to comments and README files
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2013-12-16 11:13:55 -06:00 |
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crt0.c
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ARMv7-A: Modify up_fullcontextrestore() for CONFIG_BUILD_KERNEL. It changed CPSR while in kernel. That will crash is the new CPSR is user mode while executing in kernel space. Fixed by adding a SYS_context_restore system call. There is an alternative, simpler modification to up_fullcontextrestore() that could have been done: It might have been possible to use the SPSR instead of the CPRSR and then do an exception return from up_fullcontextrestore(). That would be more efficient, but I never tried it.
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2014-09-12 08:04:27 -06:00 |
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fpu.h
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SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor
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2013-07-21 17:08:40 -06:00 |
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Kconfig
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After cached related fix, the ELF example is now functional
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2014-08-24 14:12:45 -06:00 |
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l2cc_pl310.h
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arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.
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2014-07-26 16:50:08 -06:00 |
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l2cc.h
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ARM: Move L2 cache initialization to much later in the sequence
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2014-07-27 10:03:33 -06:00 |
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mmu.h
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SAMA5D4-EK: In kernel build with address environment, need logic to map user virtual addresses to physical addresses, and vice versa
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2014-09-07 19:25:30 -06:00 |
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pginline.h
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SAMA5D4-EK: These configurations now use the fixed DRAM mapping for manipulating the page memory pool.
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2014-09-10 08:44:09 -06:00 |
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sctlr.h
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More trailing whilespace removal
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2014-04-13 16:22:22 -06:00 |
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svcall.h
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ARMv7-A: Modify up_fullcontextrestore() for CONFIG_BUILD_KERNEL. It changed CPSR while in kernel. That will crash is the new CPSR is user mode while executing in kernel space. Fixed by adding a SYS_context_restore system call. There is an alternative, simpler modification to up_fullcontextrestore() that could have been done: It might have been possible to use the SPSR instead of the CPRSR and then do an exception return from up_fullcontextrestore(). That would be more efficient, but I never tried it.
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2014-09-12 08:04:27 -06:00 |
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Toolchain.defs
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The optimization level can now be selected as part of the configuration
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2014-01-24 07:45:35 -06:00 |
