f57ba50c9b
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2215 42af7a65-404d-4744-a932-0658087f49c3
3584 lines
105 KiB
C
3584 lines
105 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32_usbdev.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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* - RM0008 Reference manual, STMicro document ID 13902
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* - STM32F10xxx USB development kit, UM0424, STMicro
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/usb.h>
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#include <nuttx/usbdev.h>
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#include <nuttx/usbdev_trace.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "stm32_internal.h"
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#include "stm32_usbdev.h"
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#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifndef CONFIG_USBDEV_EP0_MAXSIZE
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# define CONFIG_USBDEV_EP0_MAXSIZE 64
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#endif
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#ifndef CONFIG_USBDEV_MAXPOWER
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# define CONFIG_USBDEV_MAXPOWER 100 /* mA */
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#endif
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#define USB_SLOW_INT USBDEV_DEVINT_EPSLOW
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#define USB_DEVSTATUS_INT USBDEV_DEVINT_DEVSTAT
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#ifdef CONFIG_STM32_USBDEV_EPFAST_INTERRUPT
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# define USB_FAST_INT USBDEV_DEVINT_EPFAST
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#else
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# define USB_FAST_INT 0
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#endif
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#ifndef CONFIG_USB_PRI
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# define CONFIG_USB_PRI NVIC_SYSH_PRIORITY_DEFAULT
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#endif
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/* Extremely detailed register debug that you would normally never want
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* enabled.
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*/
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#ifndef CONFIG_DEBUG
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# undef CONFIG_STM32_USBDEV_REGDEBUG
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#endif
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/* Initial interrupt mask: Reset + Suspend + Correct Transfer */
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#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM)
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/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8
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* bidirectional endpoints. However, when you take into account PMA buffer
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* usage (see below) and the fact that EP0 is bidirectional, then there is
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* a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll
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* define STM32_NENDPOINTS to be 8, however, because that is how many
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* endpoint register sets there are.
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*/
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#define STM32_NENDPOINTS (8)
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#define EP0 (0)
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#define EP1 (1)
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#define EP2 (2)
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#define EP3 (3)
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#define EP4 (4)
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#define EP5 (5)
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#define EP6 (6)
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#define EP7 (7)
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#define STM32_ENDP_BIT(ep) (1 << (ep))
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#define STM32_ENDP_ALLSET 0xff
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/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */
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#define STM32_MAXPACKET_SHIFT (6)
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#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT))
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#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1)
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#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE
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/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB
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* memory. The buffer table is positioned at the beginning of the 512-byte
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* CAN/USB memory. We will use the first STM32_NENDPOINTS*4 words for the buffer
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* table. That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers.
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*/
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#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */
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#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */
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#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE)
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/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then
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* we have space for only 7 buffers; endpoint 0 will require two buffers, leaving
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* 5 for other endpoints.
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*/
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#define STM32_BUFFER_START STM32_BTABLE_SIZE
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#define STM32_EP0_RXADDR STM32_BUFFER_START
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#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET)
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#warning "Doesn't the buffer size need to include 2 bytes for the CRC?"
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#define STM32_BUFFER_EP0 0x03
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#define STM32_NBUFFERS 7
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#define STM32_BUFFER_BIT(bn) (1 << (bn))
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#define STM32_BUFFER_ALLSET 0x7f
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#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<<STM32_MAXPACKET_SHIFT))
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/* USB-related masks */
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#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)
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/* Endpoint rister masks (handling toggle fields) */
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#define EPR_NOTOG_MASK (USB_EPR_CTR_RX | USB_EPR_SETUP | USB_EPR_EPTYPE_MASK |\
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USB_EPR_EP_KIND | USB_EPR_CTR_TX | USB_EPR_EA_MASK)
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#define EPR_TXDTOG_MASK (USB_EPR_STATTX_MASK | EPR_NOTOG_MASK)
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#define EPR_RXDTOG_MASK (USB_EPR_STATRX_MASK | EPR_NOTOG_MASK)
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/* Request queue operations *************************************************/
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#define stm32_rqempty(ep) ((ep)->head == NULL)
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#define stm32_rqpeek(ep) ((ep)->head)
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/* USB trace ****************************************************************/
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/* Trace error codes */
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#define STM32_TRACEERR_ALLOCFAIL 0x0001
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#define STM32_TRACEERR_BADCLEARFEATURE 0x0002
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#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003
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#define STM32_TRACEERR_BADEPGETSTATUS 0x0004
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#define STM32_TRACEERR_BADEPNO 0x0005
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#define STM32_TRACEERR_BADEPTYPE 0x0006
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#define STM32_TRACEERR_BADGETCONFIG 0x0007
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#define STM32_TRACEERR_BADGETSETDESC 0x0008
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#define STM32_TRACEERR_BADGETSTATUS 0x0009
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#define STM32_TRACEERR_BADSETADDRESS 0x000a
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#define STM32_TRACEERR_BADSETCONFIG 0x000b
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#define STM32_TRACEERR_BADSETFEATURE 0x000c
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#define STM32_TRACEERR_BINDFAILED 0x000d
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#define STM32_TRACEERR_DISPATCHSTALL 0x000e
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#define STM32_TRACEERR_DRIVER 0x000f
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#define STM32_TRACEERR_DRIVERREGISTERED 0x0010
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#define STM32_TRACEERR_EP0BADCTR 0x0011
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#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012
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#define STM32_TRACEERR_EPBUFFER 0x0013
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#define STM32_TRACEERR_EPDISABLED 0x0014
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#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015
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#define STM32_TRACEERR_EPRESERVE 0x0016
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#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017
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#define STM32_TRACEERR_INVALIDPARMS 0x0018
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#define STM32_TRACEERR_IRQREGISTRATION 0x0019
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#define STM32_TRACEERR_NOTCONFIGURED 0x001a
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#define STM32_TRACEERR_REQABORTED 0x001b
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/* Trace interrupt codes */
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#define STM32_TRACEINTID_CLEARFEATURE 0x0001
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#define STM32_TRACEINTID_DEVGETSTATUS 0x0002
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#define STM32_TRACEINTID_DISPATCH 0x0003
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#define STM32_TRACEINTID_EP0IN 0x0004
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#define STM32_TRACEINTID_EP0INDONE 0x0005
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#define STM32_TRACEINTID_EP0OUTDONE 0x0006
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#define STM32_TRACEINTID_EP0SETUPDONE 0x0007
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#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008
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#define STM32_TRACEINTID_EPGETSTATUS 0x0009
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#define STM32_TRACEINTID_EPINDONE 0x000a
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#define STM32_TRACEINTID_EPINQEMPTY 0x000b
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#define STM32_TRACEINTID_EPOUTDONE 0x000c
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#define STM32_TRACEINTID_EPOUTPENDING 0x000d
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#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e
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#define STM32_TRACEINTID_ESOF 0x000f
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#define STM32_TRACEINTID_GETCONFIG 0x0010
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#define STM32_TRACEINTID_GETSETDESC 0x0011
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#define STM32_TRACEINTID_GETSETIF 0x0012
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#define STM32_TRACEINTID_GETSTATUS 0x0013
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#define STM32_TRACEINTID_HPINTERRUPT 0x0014
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#define STM32_TRACEINTID_IFGETSTATUS 0x0015
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#define STM32_TRACEINTID_LPCTR 0x0016
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#define STM32_TRACEINTID_LPINTERRUPT 0x0017
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#define STM32_TRACEINTID_NOSTDREQ 0x0018
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#define STM32_TRACEINTID_RESET 0x0019
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#define STM32_TRACEINTID_SETCONFIG 0x001a
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#define STM32_TRACEINTID_SETFEATURE 0x001b
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#define STM32_TRACEINTID_SUSP 0x001c
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#define STM32_TRACEINTID_SYNCHFRAME 0x001d
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#define STM32_TRACEINTID_WKUP 0x001e
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/* Ever-present MIN and MAX macros */
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#ifndef MIN
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# define MIN(a,b) (a < b ? a : b)
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#endif
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#ifndef MAX
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# define MAX(a,b) (a > b ? a : b)
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#endif
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/* Byte ordering in host-based values */
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#ifdef CONFIG_ENDIAN_BIG
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# define LSB 1
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# define MSB 0
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#else
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# define LSB 0
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# define MSB 1
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#endif
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/****************************************************************************
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* Private Type Definitions
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****************************************************************************/
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/* The various states of a control pipe */
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enum stm32_devstate_e
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{
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DEVSTATE_IDLE = 0, /* No request in progress */
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DEVSTATE_RDREQUEST, /* Read request in progress */
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DEVSTATE_WRREQUEST, /* Write request in progress */
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DEVSTATE_STALLED /* We are stalled */
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};
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/* Resume states */
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enum stm32_rsmstate_e
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{
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RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */
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RSMSTATE_STARTED, /* Resume sequence has been started */
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RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */
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};
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union wb_u
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{
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uint16 w;
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ubyte b[2];
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};
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/* A container for a request so that the request make be retained in a list */
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struct stm32_req_s
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{
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struct usbdev_req_s req; /* Standard USB request */
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struct stm32_req_s *flink; /* Supports a singly linked list */
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};
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/* This is the internal representation of an endpoint */
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struct stm32_ep_s
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{
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/* Common endpoint fields. This must be the first thing defined in the
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* structure so that it is possible to simply cast from struct usbdev_ep_s
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* to struct stm32_ep_s.
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*/
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struct usbdev_ep_s ep; /* Standard endpoint structure */
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/* STR71X-specific fields */
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struct stm32_usbdev_s *dev; /* Reference to private driver data */
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struct stm32_req_s *head; /* Request list for this endpoint */
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struct stm32_req_s *tail;
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ubyte bufno; /* Allocated buffer number */
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ubyte stalled:1; /* TRUE: Endpoint is stalled */
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ubyte halted:1; /* TRUE: Endpoint feature halted */
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ubyte txbusy:1; /* TRUE: TX endpoint FIFO full */
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ubyte txnullpkt:1; /* Null packet needed at end of transfer */
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};
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struct stm32_usbdev_s
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{
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/* Common device fields. This must be the first thing defined in the
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* structure so that it is possible to simply cast from struct usbdev_s
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* to structstm32_usbdev_s.
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*/
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struct usbdev_s usbdev;
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/* The bound device class driver */
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struct usbdevclass_driver_s *driver;
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/* STM32-specific fields */
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struct usb_ctrlreq_s ctrl; /* Last EP0 request */
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ubyte devstate; /* Driver state (see enum stm32_devstate_e) */
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ubyte rsmstate; /* Resume state (see enum stm32_rsmstate_e) */
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ubyte nesofs; /* ESOF counter (for resume support) */
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ubyte rxpending:1; /* 1: OUT data in PMA, but no read requests */
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ubyte selfpowered:1; /* 1: Device is self powered */
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ubyte epavail; /* Bitset of available endpoints */
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ubyte bufavail; /* Bitset of available buffers */
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uint16 rxstatus; /* Saved during interrupt processing */
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uint16 txstatus; /* " " " " " " " " */
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uint16 imask; /* Current interrupt mask */
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/* The endpoint list */
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struct stm32_ep_s eplist[STM32_NENDPOINTS];
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Register operations ******************************************************/
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#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
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static uint16 stm32_getreg(uint32 addr);
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static void stm32_putreg(uint16 val, uint32 addr);
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static void stm32_checksetup(void);
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static void stm32_dumpep(int epno);
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#else
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# define stm32_getreg(addr) getreg16(addr)
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# define stm32_putreg(val,addr) putreg16(val,addr)
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# define stm32_checksetup()
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# define stm32_dumpep(epno)
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#endif
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/* Low-Level Helpers ********************************************************/
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static inline void
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stm32_seteptxcount(ubyte epno, uint16 count);
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static inline void
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stm32_seteptxaddr(ubyte epno, uint16 addr);
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static inline uint16
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stm32_geteptxaddr(ubyte epno);
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static void stm32_seteprxcount(ubyte epno, uint16 count);
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static inline uint16
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stm32_geteprxcount(ubyte epno);
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static inline void
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stm32_seteprxaddr(ubyte epno, uint16 addr);
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static inline uint16
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stm32_geteprxaddr(ubyte epno);
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static inline void
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stm32_setepaddress(ubyte epno, uint16 addr);
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static inline void
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stm32_seteptype(ubyte epno, uint16 type);
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static inline void
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stm32_seteptxaddr(ubyte epno, uint16 addr);
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static inline void
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stm32_setstatusout(ubyte epno);
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static inline void
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stm32_clrstatusout(ubyte epno);
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static void stm32_clrrxdtog(ubyte epno);
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static void stm32_clrtxdtog(ubyte epno);
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static void stm32_clrepctrrx(ubyte epno);
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static void stm32_clrepctrtx(ubyte epno);
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static void stm32_seteptxstatus(ubyte epno, uint16 state);
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static void stm32_seteprxstatus(ubyte epno, uint16 state);
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static inline uint16
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stm32_geteptxstatus(ubyte epno);
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static inline uint16
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stm32_geteprxstatus(ubyte epno);
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static uint16 stm32_eptxstalled(ubyte epno);
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static uint16 stm32_eprxstalled(ubyte epno);
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static void stm32_setimask(struct stm32_usbdev_s *priv, uint16 setbits,
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uint16 clrbits);
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/* Suspend/Resume Helpers ***************************************************/
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static void stm32_suspend(struct stm32_usbdev_s *priv);
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static void stm32_initresume(struct stm32_usbdev_s *priv);
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static void stm32_esofpoll(struct stm32_usbdev_s *priv) ;
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/* Request Helpers **********************************************************/
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static void stm32_copytopma(const ubyte *buffer, uint16 pma,
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uint16 nbytes);
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static inline void
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stm32_copyfrompma(ubyte *buffer, uint16 pma, uint16 nbytes);
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static struct stm32_req_s *
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stm32_rqdequeue(struct stm32_ep_s *privep);
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static void stm32_rqenqueue(struct stm32_ep_s *privep,
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struct stm32_req_s *req);
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static inline void
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stm32_abortrequest(struct stm32_ep_s *privep,
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struct stm32_req_s *privreq, sint16 result);
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static void stm32_reqcomplete(struct stm32_ep_s *privep, sint16 result);
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static void stm32_epwrite(struct stm32_usbdev_s *buf,
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struct stm32_ep_s *privep, const ubyte *data, uint32 nbytes);
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static int stm32_wrrequest(struct stm32_usbdev_s *priv,
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struct stm32_ep_s *privep);
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static int stm32_rdrequest(struct stm32_usbdev_s *priv,
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struct stm32_ep_s *privep);
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/* Interrupt level processing ***********************************************/
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static void stm32_dispatchrequest(struct stm32_usbdev_s *priv);
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static void stm32_epdone(struct stm32_usbdev_s *priv, ubyte epno);
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static void stm32_setdevaddr(struct stm32_usbdev_s *priv, ubyte value);
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static void stm32_ep0setup(struct stm32_usbdev_s *priv);
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static void stm32_ep0out(struct stm32_usbdev_s *priv);
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static void stm32_ep0in(struct stm32_usbdev_s *priv);
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static inline void
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stm32_ep0done(struct stm32_usbdev_s *priv, uint16 istr);
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static void stm32_lptransfer(struct stm32_usbdev_s *priv);
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static int stm32_hpinterrupt(int irq, void *context);
|
|
static int stm32_lpinterrupt(int irq, void *context);
|
|
|
|
/* Endpoint helpers *********************************************************/
|
|
|
|
static inline struct stm32_ep_s *
|
|
stm32_epreserve(struct stm32_usbdev_s *priv, ubyte epset);
|
|
static inline void
|
|
stm32_epunreserve(struct stm32_usbdev_s *priv,
|
|
struct stm32_ep_s *privep);
|
|
static inline boolean
|
|
stm32_epreserved(struct stm32_usbdev_s *priv, int epno);
|
|
static int stm32_epallocpma(struct stm32_usbdev_s *priv);
|
|
static inline void
|
|
stm32_epfreepma(struct stm32_usbdev_s *priv,
|
|
struct stm32_ep_s *privep);
|
|
|
|
/* Endpoint operations ******************************************************/
|
|
|
|
static int stm32_epconfigure(struct usbdev_ep_s *ep,
|
|
const struct usb_epdesc_s *desc, boolean last);
|
|
static int stm32_epdisable(struct usbdev_ep_s *ep);
|
|
static struct usbdev_req_s *
|
|
stm32_epallocreq(struct usbdev_ep_s *ep);
|
|
static void stm32_epfreereq(struct usbdev_ep_s *ep,
|
|
struct usbdev_req_s *);
|
|
static int stm32_epsubmit(struct usbdev_ep_s *ep,
|
|
struct usbdev_req_s *req);
|
|
static int stm32_epcancel(struct usbdev_ep_s *ep,
|
|
struct usbdev_req_s *req);
|
|
static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume);
|
|
|
|
/* USB device controller operations *****************************************/
|
|
|
|
static struct usbdev_ep_s *
|
|
stm32_allocep(struct usbdev_s *dev, ubyte epno, boolean in,
|
|
ubyte eptype);
|
|
static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep);
|
|
static int stm32_getframe(struct usbdev_s *dev);
|
|
static int stm32_wakeup(struct usbdev_s *dev);
|
|
static int stm32_selfpowered(struct usbdev_s *dev, boolean selfpowered);
|
|
|
|
/* Initialization/Reset *****************************************************/
|
|
|
|
static void stm32_reset(struct stm32_usbdev_s *priv);
|
|
static void stm32_hwreset(struct stm32_usbdev_s *priv);
|
|
|
|
/****************************************************************************
|
|
* Private Data
|
|
****************************************************************************/
|
|
|
|
/* Since there is only a single USB interface, all status information can be
|
|
* be simply retained in a single global instance.
|
|
*/
|
|
|
|
static struct stm32_usbdev_s g_usbdev;
|
|
|
|
static const struct usbdev_epops_s g_epops =
|
|
{
|
|
.configure = stm32_epconfigure,
|
|
.disable = stm32_epdisable,
|
|
.allocreq = stm32_epallocreq,
|
|
.freereq = stm32_epfreereq,
|
|
.submit = stm32_epsubmit,
|
|
.cancel = stm32_epcancel,
|
|
.stall = stm32_epstall,
|
|
};
|
|
|
|
static const struct usbdev_ops_s g_devops =
|
|
{
|
|
.allocep = stm32_allocep,
|
|
.freeep = stm32_freeep,
|
|
.getframe = stm32_getframe,
|
|
.wakeup = stm32_wakeup,
|
|
.selfpowered = stm32_selfpowered,
|
|
.pullup = stm32_usbpullup,
|
|
};
|
|
|
|
/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Private Private Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Register Operations
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_getreg
|
|
****************************************************************************/
|
|
|
|
#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
|
|
static uint16 stm32_getreg(uint32 addr)
|
|
{
|
|
static uint32 prevaddr = 0;
|
|
static uint16 preval = 0;
|
|
static uint32 count = 0;
|
|
|
|
/* Read the value from the register */
|
|
|
|
uint16 val = getreg16(addr);
|
|
|
|
/* Is this the same value that we read from the same register last time?
|
|
* Are we polling the register? If so, suppress some of the output.
|
|
*/
|
|
|
|
if (addr == prevaddr && val == preval)
|
|
{
|
|
if (count == 0xffffffff || ++count > 3)
|
|
{
|
|
if (count == 4)
|
|
{
|
|
lldbg("...\n");
|
|
}
|
|
return val;
|
|
}
|
|
}
|
|
|
|
/* No this is a new address or value */
|
|
|
|
else
|
|
{
|
|
/* Did we print "..." for the previous value? */
|
|
|
|
if (count > 3)
|
|
{
|
|
/* Yes.. then show how many times the value repeated */
|
|
|
|
lldbg("[repeats %d more times]\n", count-3);
|
|
}
|
|
|
|
/* Save the new address, value, and count */
|
|
|
|
prevaddr = addr;
|
|
preval = val;
|
|
count = 1;
|
|
}
|
|
|
|
/* Show the register value read */
|
|
|
|
lldbg("%08x->%04x\n", addr, val);
|
|
return val;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_putreg
|
|
****************************************************************************/
|
|
|
|
#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
|
|
static void stm32_putreg(uint16 val, uint32 addr)
|
|
{
|
|
/* Show the register value being written */
|
|
|
|
lldbg("%08x<-%04x\n", addr, val);
|
|
|
|
/* Write the value */
|
|
|
|
putreg32(val, addr);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dumpep
|
|
****************************************************************************/
|
|
|
|
#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
|
|
static void stm32_dumpep(int epno)
|
|
{
|
|
uint32 addr;
|
|
|
|
/* Common registers */
|
|
|
|
lldbg("CNTR: %04x\n", getreg16(STM32_USB_CNTR));
|
|
lldbg("ISTR: %04x\n", getreg16(STM32_USB_ISTR));
|
|
lldbg("FNR: %04x\n", getreg16(STM32_USB_FNR));
|
|
lldbg("DADDR: %04x\n", getreg16(STM32_USB_DADDR));
|
|
lldbg("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE));
|
|
|
|
/* Endpoint register */
|
|
|
|
addr = STM32_USB_EPR(epno);
|
|
lldbg("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr));
|
|
|
|
/* Endpoint descriptor */
|
|
|
|
addr = STM32_USB_BTABLE_ADDR(epno, 0);
|
|
lldbg("DESC: %08x\n", addr);
|
|
|
|
/* Endpoint buffer descriptor */
|
|
|
|
addr = STM32_USB_ADDR_TX(epno);
|
|
lldbg(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr));
|
|
|
|
addr = STM32_USB_COUNT_TX(epno);
|
|
lldbg(" COUNT: [%08x] %04x\n", addr, getreg16(addr));
|
|
|
|
addr = STM32_USB_ADDR_RX(epno);
|
|
lldbg(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr));
|
|
|
|
addr = STM32_USB_COUNT_RX(epno);
|
|
lldbg(" COUNT: [%08x] %04x\n", addr, getreg16(addr));
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_checksetup
|
|
****************************************************************************/
|
|
|
|
#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
|
|
static void stm32_checksetup(void)
|
|
{
|
|
uint32 cfgr = getreg32(STM32_RCC_CFGR);
|
|
uint32 apb1rstr = getreg32(STM32_RCC_APB1RSTR);
|
|
uint32 apb1enr = getreg32(STM32_RCC_APB1ENR);
|
|
|
|
lldbg("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr);
|
|
|
|
if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 ||
|
|
(apb1enr & RCC_APB1ENR_USBEN) == 0)
|
|
{
|
|
lldbg("ERROR: USB is NOT setup correctly\n");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Low-Level Helpers
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_seteptxcount
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_seteptxcount(ubyte epno, uint16 count)
|
|
{
|
|
volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_TX(epno);
|
|
*epaddr = count;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteptxaddr
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_seteptxaddr(ubyte epno, uint16 addr)
|
|
{
|
|
volatile uint32 *txaddr = (uint32*)STM32_USB_ADDR_TX(epno);
|
|
*txaddr = addr;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_geteptxaddr
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_geteptxaddr(ubyte epno)
|
|
{
|
|
volatile uint32 *txaddr = (uint32*)STM32_USB_ADDR_TX(epno);
|
|
return (uint16)*txaddr;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteprxcount
|
|
****************************************************************************/
|
|
|
|
static void stm32_seteprxcount(ubyte epno, uint16 count)
|
|
{
|
|
volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_RX(epno);
|
|
uint16 nblocks;
|
|
|
|
/* The upper bits of the RX COUNT value contain the size of allocated
|
|
* RX buffer. This is based on a block size of 2 or 32:
|
|
*
|
|
* USB_COUNT_RX_BL_SIZE not set:
|
|
* nblocks is in units of 2 bytes.
|
|
* 00000 - not allowed
|
|
* 00001 - 2 bytes
|
|
* ....
|
|
* 11111 - 62 bytes
|
|
*
|
|
* USB_COUNT_RX_BL_SIZE set:
|
|
* 00000 - 32 bytes
|
|
* 00001 - 64 bytes
|
|
* ...
|
|
* 01111 - 512 bytes
|
|
* 1xxxx - Not allowed
|
|
*/
|
|
|
|
if (count > 62)
|
|
{
|
|
/* Blocks of 32 (with 0 meaning one block of 32) */
|
|
|
|
nblocks = (count >> 5) - 1 ;
|
|
DEBUGASSERT(nblocks <= 0x0f);
|
|
*epaddr = (uint32)((nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE);
|
|
}
|
|
else
|
|
{
|
|
/* Blocks of 2 (with 1 meaning one block of 2) */
|
|
|
|
nblocks = (count + 1) >> 1;
|
|
DEBUGASSERT(nblocks > 0 && nblocks < 0x1f);
|
|
*epaddr = (uint32)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_geteprxcount
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_geteprxcount(ubyte epno)
|
|
{
|
|
volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_RX(epno);
|
|
return (*epaddr) & USB_COUNT_RX_MASK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteprxaddr
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_seteprxaddr(ubyte epno, uint16 addr)
|
|
{
|
|
volatile uint32 *rxaddr = (uint32*)STM32_USB_ADDR_RX(epno);
|
|
*rxaddr = addr;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteprxaddr
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_geteprxaddr(ubyte epno)
|
|
{
|
|
volatile uint32 *rxaddr = (uint32*)STM32_USB_ADDR_RX(epno);
|
|
return (uint16)*rxaddr;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_setepaddress
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_setepaddress(ubyte epno, uint16 addr)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval &= ~USB_EPR_EA_MASK;
|
|
regval |= (addr << USB_EPR_EA_SHIFT);
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteptype
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_seteptype(ubyte epno, uint16 type)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval &= ~USB_EPR_EPTYPE_MASK;
|
|
regval |= type;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_setstatusout
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_setstatusout(ubyte epno)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
/* For a BULK endpoint the EP_KIND bit is used to enabled double buffering;
|
|
* for a CONTROL endpoint, it is set to indicate that a status OUT
|
|
* transaction is expected. The bit is not used with out endpoint types.
|
|
*/
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval |= USB_EPR_EP_KIND;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_clrstatusout
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_clrstatusout(ubyte epno)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
/* For a BULK endpoint the EP_KIND bit is used to enabled double buffering;
|
|
* for a CONTROL endpoint, it is set to indicate that a status OUT
|
|
* transaction is expected. The bit is not used with out endpoint types.
|
|
*/
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval &= ~USB_EPR_EP_KIND;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_clrrxdtog
|
|
****************************************************************************/
|
|
|
|
static void stm32_clrrxdtog(ubyte epno)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
if ((regval & USB_EPR_DTOG_RX) != 0)
|
|
{
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval |= USB_EPR_DTOG_RX;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_clrtxdtog
|
|
****************************************************************************/
|
|
|
|
static void stm32_clrtxdtog(ubyte epno)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
if ((regval & USB_EPR_DTOG_TX) != 0)
|
|
{
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval |= USB_EPR_DTOG_TX;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_clrepctrrx
|
|
****************************************************************************/
|
|
|
|
static void stm32_clrepctrrx(ubyte epno)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval &= ~USB_EPR_CTR_RX;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_clrepctrtx
|
|
****************************************************************************/
|
|
|
|
static void stm32_clrepctrtx(ubyte epno)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr);
|
|
regval &= EPR_NOTOG_MASK;
|
|
regval &= ~USB_EPR_CTR_TX;
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_geteptxstatus
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_geteptxstatus(ubyte epno)
|
|
{
|
|
return (uint16)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_geteprxstatus
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_geteprxstatus(ubyte epno)
|
|
{
|
|
return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteptxstatus
|
|
****************************************************************************/
|
|
|
|
static void stm32_seteptxstatus(ubyte epno, uint16 state)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr) & EPR_TXDTOG_MASK;
|
|
|
|
/* Toggle first bit */
|
|
|
|
if ((USB_EPR_STATTX_DTOG1 & state) != 0)
|
|
{
|
|
regval ^= USB_EPR_STATTX_DTOG1;
|
|
}
|
|
|
|
/* Toggle second bit */
|
|
|
|
if ((USB_EPR_STATTX_DTOG2 & state) != 0)
|
|
{
|
|
regval ^= USB_EPR_STATTX_DTOG2;
|
|
}
|
|
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_seteprxstatus
|
|
****************************************************************************/
|
|
|
|
static void stm32_seteprxstatus(ubyte epno, uint16 state)
|
|
{
|
|
uint32 epaddr = STM32_USB_EPR(epno);
|
|
uint16 regval;
|
|
|
|
regval = stm32_getreg(epaddr) & EPR_RXDTOG_MASK;
|
|
|
|
/* Toggle first bit */
|
|
|
|
if ((USB_EPR_STATRX_DTOG1 & state) != 0)
|
|
{
|
|
regval ^= USB_EPR_STATRX_DTOG1;
|
|
}
|
|
|
|
/* Toggle second bit */
|
|
|
|
if ((USB_EPR_STATRX_DTOG2 & state) != 0)
|
|
{
|
|
regval ^= USB_EPR_STATRX_DTOG2;
|
|
}
|
|
|
|
stm32_putreg(regval, epaddr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_eptxstalled
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_eptxstalled(ubyte epno)
|
|
{
|
|
return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_eprxstalled
|
|
****************************************************************************/
|
|
|
|
static inline uint16 stm32_eprxstalled(ubyte epno)
|
|
{
|
|
return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Request Helpers
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_copytopma
|
|
****************************************************************************/
|
|
|
|
static void stm32_copytopma(const ubyte *buffer, uint16 pma, uint16 nbytes)
|
|
{
|
|
uint16 *dest;
|
|
uint16 ms;
|
|
uint16 ls;
|
|
int nwords = (nbytes + 1) >> 1;
|
|
int i;
|
|
|
|
/* Copy loop. Source=user buffer, Dest=packet memory */
|
|
|
|
dest = (uint16*)(STM32_USBCANRAM_BASE + ((uint32)pma << 1));
|
|
for (i = nwords; i != 0; i--)
|
|
{
|
|
/* Read two bytes and pack into on 16-bit word */
|
|
|
|
ls = (uint16)(*buffer++);
|
|
ms = (uint16)(*buffer++);
|
|
*dest = ms << 8 | ls;
|
|
|
|
/* Source address increments by 2*sizeof(ubyte) = 2; Dest address
|
|
* increments by 2*sizeof(uint16) = 4.
|
|
*/
|
|
|
|
dest += 2;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_copyfrompma
|
|
****************************************************************************/
|
|
|
|
static inline void
|
|
stm32_copyfrompma(ubyte *buffer, uint16 pma, uint16 nbytes)
|
|
{
|
|
uint32 *src;
|
|
int nwords = (nbytes + 1) >> 1;
|
|
int i;
|
|
|
|
/* Copy loop. Source=packet memory, Dest=user buffer */
|
|
|
|
src = (uint32*)(STM32_USBCANRAM_BASE + ((uint32)pma << 1));
|
|
for (i = nwords; i != 0; i--)
|
|
{
|
|
/* Copy 16-bits from packet memory to user buffer. */
|
|
|
|
*(uint16*)buffer = *src++;
|
|
|
|
/* Source address increments by 1*sizeof(uint32) = 4; Dest address
|
|
* increments by 2*sizeof(ubyte) = 2.
|
|
*/
|
|
|
|
buffer += 2;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rqdequeue
|
|
****************************************************************************/
|
|
|
|
static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep)
|
|
{
|
|
struct stm32_req_s *ret = privep->head;
|
|
|
|
if (ret)
|
|
{
|
|
privep->head = ret->flink;
|
|
if (!privep->head)
|
|
{
|
|
privep->tail = NULL;
|
|
}
|
|
|
|
ret->flink = NULL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rqenqueue
|
|
****************************************************************************/
|
|
|
|
static void stm32_rqenqueue(struct stm32_ep_s *privep,
|
|
struct stm32_req_s *req)
|
|
{
|
|
req->flink = NULL;
|
|
if (!privep->head)
|
|
{
|
|
privep->head = req;
|
|
privep->tail = req;
|
|
}
|
|
else
|
|
{
|
|
privep->tail->flink = req;
|
|
privep->tail = req;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_abortrequest
|
|
****************************************************************************/
|
|
|
|
static inline void
|
|
stm32_abortrequest(struct stm32_ep_s *privep, struct stm32_req_s *privreq, sint16 result)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16)USB_EPNO(privep->ep.eplog));
|
|
|
|
/* Save the result in the request structure */
|
|
|
|
privreq->req.result = result;
|
|
|
|
/* Callback to the request completion handler */
|
|
|
|
privreq->req.callback(&privep->ep, &privreq->req);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_reqcomplete
|
|
****************************************************************************/
|
|
|
|
static void stm32_reqcomplete(struct stm32_ep_s *privep, sint16 result)
|
|
{
|
|
struct stm32_req_s *privreq;
|
|
irqstate_t flags;
|
|
|
|
/* Remove the completed request at the head of the endpoint request list */
|
|
|
|
flags = irqsave();
|
|
privreq = stm32_rqdequeue(privep);
|
|
irqrestore(flags);
|
|
|
|
if (privreq)
|
|
{
|
|
/* If endpoint 0, temporarily reflect the state of protocol stalled
|
|
* in the callback.
|
|
*/
|
|
|
|
boolean stalled = privep->stalled;
|
|
if (USB_EPNO(privep->ep.eplog) == EP0)
|
|
{
|
|
privep->stalled = (privep->dev->devstate == DEVSTATE_STALLED);
|
|
}
|
|
|
|
/* Save the result in the request structure */
|
|
|
|
privreq->req.result = result;
|
|
|
|
/* Callback to the request completion handler */
|
|
|
|
privreq->flink = NULL;
|
|
privreq->req.callback(&privep->ep, &privreq->req);
|
|
|
|
/* Restore the stalled indication */
|
|
|
|
privep->stalled = stalled;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tm32_epwrite
|
|
****************************************************************************/
|
|
|
|
static void stm32_epwrite(struct stm32_usbdev_s *priv,
|
|
struct stm32_ep_s *privep,
|
|
const ubyte *buf, uint32 nbytes)
|
|
{
|
|
ubyte epno = USB_EPNO(privep->ep.eplog);
|
|
usbtrace(TRACE_WRITE(epno), nbytes);
|
|
|
|
/* Check for a zero-length packet */
|
|
|
|
if (nbytes > 0)
|
|
{
|
|
/* Copy the data from the user buffer into packet memory for this
|
|
* endpoint
|
|
*/
|
|
|
|
stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes);
|
|
}
|
|
|
|
/* Send the packet (might be a null packet nbytes == 0) */
|
|
|
|
stm32_seteptxcount(epno, nbytes);
|
|
priv->txstatus = USB_EPR_STATTX_VALID;
|
|
|
|
/* Indicate that there is data in the TX packet memory. This will be cleared
|
|
* when the next data out interrupt is received.
|
|
*/
|
|
|
|
privep->txbusy = TRUE;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_wrrequest
|
|
****************************************************************************/
|
|
|
|
static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep)
|
|
{
|
|
struct stm32_req_s *privreq;
|
|
ubyte *buf;
|
|
ubyte epno;
|
|
int nbytes;
|
|
int bytesleft;
|
|
|
|
/* We get here when an IN endpoint interrupt occurs. So now we know that
|
|
* there is no TX transfer in progress.
|
|
*/
|
|
|
|
privep->txbusy = FALSE;
|
|
|
|
/* Check the request from the head of the endpoint request queue */
|
|
|
|
privreq = stm32_rqpeek(privep);
|
|
if (!privreq)
|
|
{
|
|
/* There is no TX transfer in progress and no new pending TX
|
|
* requests to send... STALL the TX status.
|
|
*/
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0);
|
|
priv->devstate = DEVSTATE_IDLE;
|
|
return OK;
|
|
}
|
|
|
|
epno = USB_EPNO(privep->ep.eplog);
|
|
ullvdbg("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
|
|
epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
|
|
|
|
/* Get the number of bytes left to be sent in the packet */
|
|
|
|
bytesleft = privreq->req.len - privreq->req.xfrd;
|
|
nbytes = bytesleft;
|
|
|
|
#warning "REVISIT: If the EP supports double buffering, then we can do better"
|
|
|
|
/* Send the next packet */
|
|
|
|
if (nbytes > 0)
|
|
{
|
|
/* Either send the maxpacketsize or all of the remaining data in
|
|
* the request.
|
|
*/
|
|
|
|
privep->txnullpkt = 0;
|
|
if (nbytes >= privep->ep.maxpacket)
|
|
{
|
|
nbytes = privep->ep.maxpacket;
|
|
|
|
/* Handle the case where this packet is exactly the
|
|
* maxpacketsize. Do we need to send a zero-length packet
|
|
* in this case?
|
|
*/
|
|
|
|
if (bytesleft == privep->ep.maxpacket &&
|
|
(privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
|
|
{
|
|
privep->txnullpkt = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Send the packet (might be a null packet nbytes == 0) */
|
|
|
|
buf = privreq->req.buf + privreq->req.xfrd;
|
|
stm32_epwrite(priv, privep, buf, nbytes);
|
|
priv->devstate = DEVSTATE_WRREQUEST;
|
|
|
|
/* Update for the next data IN interrupt */
|
|
|
|
privreq->req.xfrd += nbytes;
|
|
bytesleft = privreq->req.len - privreq->req.xfrd;
|
|
|
|
/* If all of the bytes were sent (including any final null packet)
|
|
* then we are finished with the transfer
|
|
*/
|
|
|
|
if (bytesleft == 0 && !privep->txnullpkt)
|
|
{
|
|
usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
|
|
privep->txnullpkt = 0;
|
|
stm32_reqcomplete(privep, OK);
|
|
priv->devstate = DEVSTATE_IDLE;
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rdrequest
|
|
****************************************************************************/
|
|
|
|
static int stm32_rdrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep)
|
|
{
|
|
struct stm32_req_s *privreq;
|
|
uint32 src;
|
|
ubyte *dest;
|
|
ubyte epno;
|
|
int pmalen;
|
|
int readlen;
|
|
|
|
/* Check the request from the head of the endpoint request queue */
|
|
|
|
epno = USB_EPNO(privep->ep.eplog);
|
|
privreq = stm32_rqpeek(privep);
|
|
if (!privreq)
|
|
{
|
|
/* Incoming data available in PMA, but no packet to receive the data.
|
|
* Mark that the RX data is pending and hope that a packet is returned
|
|
* soon.
|
|
*/
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno);
|
|
priv->rxpending = TRUE;
|
|
return OK;
|
|
}
|
|
|
|
ullvdbg("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd);
|
|
|
|
/* Ignore any attempt to receive a zero length packet */
|
|
|
|
if (privreq->req.len == 0)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0);
|
|
stm32_reqcomplete(privep, OK);
|
|
return OK;
|
|
}
|
|
|
|
usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
|
|
|
|
/* Get the source and desintion transfer addresses */
|
|
|
|
dest = privreq->req.buf + privreq->req.xfrd;
|
|
src = stm32_geteprxaddr(epno);
|
|
|
|
/* Get the number of bytes to read from packet memory */
|
|
#warning "Doesn't this length include 2 bytes for the CRC?"
|
|
|
|
pmalen = stm32_geteprxcount(epno);
|
|
readlen = MIN(privreq->req.len, pmalen);
|
|
|
|
/* Receive the next packet */
|
|
|
|
stm32_copyfrompma(dest, src, readlen);
|
|
priv->devstate = DEVSTATE_RDREQUEST;
|
|
|
|
/* If the receive buffer is full then we are finished with the transfer */
|
|
|
|
privreq->req.xfrd += readlen;
|
|
if (privreq->req.xfrd >= privreq->req.len)
|
|
{
|
|
/* Complete the transfer and mark the state IDLE. The endpoint
|
|
* RX will be marked valid when the data phase completes.
|
|
*/
|
|
|
|
usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd);
|
|
stm32_reqcomplete(privep, OK);
|
|
priv->devstate = DEVSTATE_IDLE;
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_cancelrequests
|
|
****************************************************************************/
|
|
|
|
static void stm32_cancelrequests(struct stm32_ep_s *privep)
|
|
{
|
|
while (!stm32_rqempty(privep))
|
|
{
|
|
usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)),
|
|
(stm32_rqpeek(privep))->req.xfrd);
|
|
stm32_reqcomplete(privep, -ESHUTDOWN);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Interrupt Level Processing
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_dispatchrequest
|
|
****************************************************************************/
|
|
|
|
static void stm32_dispatchrequest(struct stm32_usbdev_s *priv)
|
|
{
|
|
int ret;
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0);
|
|
if (priv && priv->driver)
|
|
{
|
|
/* Forward to the control request to the class driver implementation */
|
|
|
|
ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl);
|
|
if (ret < 0)
|
|
{
|
|
/* Stall on failure */
|
|
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epdone
|
|
****************************************************************************/
|
|
|
|
static void stm32_epdone(struct stm32_usbdev_s *priv, ubyte epno)
|
|
{
|
|
struct stm32_ep_s *privep;
|
|
uint16 epr;
|
|
|
|
/* Decode and service non control endpoints interrupt */
|
|
|
|
epr = stm32_getreg(STM32_USB_EPR(epno));
|
|
privep = &priv->eplist[epno];
|
|
|
|
/* OUT: host-to-device
|
|
* CTR_RX is set by the hardware when an OUT/SETUP transaction
|
|
* successfully completed on this endpoint.
|
|
*/
|
|
|
|
if ((epr & USB_EPR_CTR_RX) != 0)
|
|
{
|
|
/* Clear interrupt status */
|
|
|
|
stm32_clrepctrrx(epno);
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epno);
|
|
|
|
/* Handle read requests: Read host data into the current read request */
|
|
|
|
priv->rxstatus = USB_EPR_STATRX_VALID;
|
|
if (!stm32_rqempty(privep))
|
|
{
|
|
stm32_rdrequest(priv, privep);
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16)epno);
|
|
priv->rxstatus = USB_EPR_STATRX_NAK;
|
|
priv->rxpending = 1;
|
|
}
|
|
|
|
/* Set the new RX status */
|
|
|
|
stm32_seteprxstatus(epno, priv->rxstatus);
|
|
}
|
|
|
|
/* IN: device-to-host
|
|
* CTR_TX is set when an IN transaction successfully completes on
|
|
* an endpoint
|
|
*/
|
|
|
|
else if ((epr & USB_EPR_CTR_TX) != 0)
|
|
{
|
|
/* Clear interrupt status */
|
|
|
|
stm32_clrepctrtx(epno);
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr);
|
|
|
|
/* Handle write requests */
|
|
|
|
priv->rxstatus = USB_EPR_STATRX_NAK;
|
|
stm32_wrrequest(priv, privep);
|
|
|
|
/* Set the new RX status */
|
|
|
|
stm32_seteptxstatus(epno, priv->txstatus);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_setdevaddr
|
|
****************************************************************************/
|
|
|
|
static void stm32_setdevaddr(struct stm32_usbdev_s *priv, ubyte value)
|
|
{
|
|
int epno;
|
|
|
|
/* Set address in every allocated endpoint */
|
|
|
|
for (epno = 0; epno < STM32_NENDPOINTS; epno++)
|
|
{
|
|
if (stm32_epreserved(priv, epno))
|
|
{
|
|
stm32_setepaddress((ubyte)epno, (ubyte)epno);
|
|
}
|
|
}
|
|
|
|
/* Set the device address and enable function */
|
|
|
|
stm32_putreg(value|USB_DADDR_EF, STM32_USB_DADDR);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_ep0setup
|
|
****************************************************************************/
|
|
|
|
static void stm32_ep0setup(struct stm32_usbdev_s *priv)
|
|
{
|
|
struct stm32_ep_s *ep0 = &priv->eplist[EP0];
|
|
struct stm32_req_s *privreq = stm32_rqpeek(ep0);
|
|
struct stm32_ep_s *privep;
|
|
union wb_u value;
|
|
union wb_u index;
|
|
union wb_u len;
|
|
union wb_u response;
|
|
boolean handled = FALSE;
|
|
ubyte epno;
|
|
int nbytes = 0; /* Assume zero-length packet */
|
|
int ret;
|
|
|
|
/* Terminate any pending requests */
|
|
|
|
while (!stm32_rqempty(ep0))
|
|
{
|
|
sint16 result = OK;
|
|
if (privreq->req.xfrd != privreq->req.len)
|
|
{
|
|
result = -EPROTO;
|
|
}
|
|
|
|
usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd);
|
|
stm32_reqcomplete(ep0, result);
|
|
}
|
|
|
|
/* Assume NOT stalled; no TX in progress */
|
|
|
|
ep0->stalled = 0;
|
|
ep0->txbusy = 0;
|
|
|
|
/* Get a 32-bit PMA address and use that to get the 8-byte setup request */
|
|
|
|
stm32_copyfrompma((ubyte*)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ);
|
|
|
|
/* And extract the little-endian 16-bit values to host order */
|
|
|
|
value.w = GETUINT16(priv->ctrl.value);
|
|
index.w = GETUINT16(priv->ctrl.index);
|
|
len.w = GETUINT16(priv->ctrl.len);
|
|
|
|
ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
|
|
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
|
|
|
|
priv->devstate = DEVSTATE_IDLE;
|
|
|
|
/* Dispatch any non-standard requests */
|
|
|
|
if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type);
|
|
|
|
/* Let the class implementation handle all non-standar requests */
|
|
|
|
stm32_dispatchrequest(priv);
|
|
return;
|
|
}
|
|
|
|
/* Handle standard request. Pick off the things of interest to the
|
|
* USB device controller driver; pass what is left to the class driver
|
|
*/
|
|
|
|
switch (priv->ctrl.req)
|
|
{
|
|
case USB_REQ_GETSTATUS:
|
|
{
|
|
/* type: device-to-host; recipient = device, interface, endpoint
|
|
* value: 0
|
|
* index: zero interface endpoint
|
|
* len: 2; data = status
|
|
*/
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), priv->ctrl.type);
|
|
if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 ||
|
|
index.b[MSB] != 0 || value.w != 0)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
else
|
|
{
|
|
switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK)
|
|
{
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
{
|
|
epno = USB_EPNO(index.b[LSB]);
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), epno);
|
|
if (epno >= STM32_NENDPOINTS)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), epno);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
else
|
|
{
|
|
privep = &priv->eplist[epno];
|
|
response.w = 0; /* Not stalled */
|
|
nbytes = 2; /* Response size: 2 bytes */
|
|
|
|
if (USB_ISEPIN(index.b[LSB]))
|
|
{
|
|
/* IN endpoint */
|
|
|
|
if (stm32_eptxstalled(epno))
|
|
{
|
|
/* IN Endpoint stalled */
|
|
|
|
response.b[LSB] = 1; /* Stalled */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* OUT endpoint */
|
|
|
|
if (stm32_eprxstalled(epno))
|
|
{
|
|
/* OUT Endpoint stalled */
|
|
|
|
response.b[LSB] = 1; /* Stalled */
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
{
|
|
if (index.w == 0)
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0);
|
|
|
|
/* Features: Remote Wakeup=YES; selfpowered=? */
|
|
|
|
response.w = 0;
|
|
response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) |
|
|
(1 << USB_FEATURE_REMOTEWAKEUP);
|
|
nbytes = 2; /* Response size: 2 bytes */
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0);
|
|
response.w = 0;
|
|
nbytes = 2; /* Response size: 2 bytes */
|
|
}
|
|
break;
|
|
|
|
default:
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_CLEARFEATURE:
|
|
{
|
|
/* type: host-to-device; recipient = device, interface or endpoint
|
|
* value: feature selector
|
|
* index: zero interface endpoint;
|
|
* len: zero, data = none
|
|
*/
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), priv->ctrl.type);
|
|
if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
|
|
{
|
|
/* Let the class implementation handle all recipients (except for the
|
|
* endpoint recipient)
|
|
*/
|
|
|
|
stm32_dispatchrequest(priv);
|
|
handled = TRUE;
|
|
}
|
|
else
|
|
{
|
|
/* Endpoint recipient */
|
|
|
|
epno = USB_EPNO(index.b[LSB]);
|
|
if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 &&
|
|
value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
|
|
{
|
|
privep = &priv->eplist[epno];
|
|
privep->halted = 0;
|
|
ret = stm32_epstall(&privep->ep, TRUE);
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_SETFEATURE:
|
|
{
|
|
/* type: host-to-device; recipient = device, interface, endpoint
|
|
* value: feature selector
|
|
* index: zero interface endpoint;
|
|
* len: 0; data = none
|
|
*/
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), priv->ctrl.type);
|
|
if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
|
|
value.w == USB_FEATURE_TESTMODE)
|
|
{
|
|
/* Special case recipient=device test mode */
|
|
|
|
ullvdbg("test mode: %d\n", index.w);
|
|
}
|
|
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
|
|
{
|
|
/* The class driver handles all recipients except recipient=endpoint */
|
|
|
|
stm32_dispatchrequest(priv);
|
|
handled = TRUE;
|
|
}
|
|
else
|
|
{
|
|
/* Handler recipient=endpoint */
|
|
|
|
epno = USB_EPNO(index.b[LSB]);
|
|
if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 &&
|
|
value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
|
|
{
|
|
privep = &priv->eplist[epno];
|
|
privep->halted = 1;
|
|
ret = stm32_epstall(&privep->ep, FALSE);
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_SETADDRESS:
|
|
{
|
|
/* type: host-to-device; recipient = device
|
|
* value: device address
|
|
* index: 0
|
|
* len: 0; data = none
|
|
*/
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), value.w);
|
|
if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE ||
|
|
index.w != 0 || len.w != 0 || value.w > 127)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
|
|
/* Note that setting of the device address will be deferred. A zero-length
|
|
* packet will be sent and the device address will be set when the zero-
|
|
* length packet transfer completes.
|
|
*/
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_GETDESCRIPTOR:
|
|
/* type: device-to-host; recipient = device
|
|
* value: descriptor type and index
|
|
* index: 0 or language ID;
|
|
* len: descriptor len; data = descriptor
|
|
*/
|
|
case USB_REQ_SETDESCRIPTOR:
|
|
/* type: host-to-device; recipient = device
|
|
* value: descriptor type and index
|
|
* index: 0 or language ID;
|
|
* len: descriptor len; data = descriptor
|
|
*/
|
|
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), priv->ctrl.type);
|
|
if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
|
|
{
|
|
/* The request seems valid... let the class implementation handle it */
|
|
|
|
stm32_dispatchrequest(priv);
|
|
handled = TRUE;
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_GETCONFIGURATION:
|
|
/* type: device-to-host; recipient = device
|
|
* value: 0;
|
|
* index: 0;
|
|
* len: 1; data = configuration value
|
|
*/
|
|
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), priv->ctrl.type);
|
|
if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
|
|
value.w == 0 && index.w == 0 && len.w == 1)
|
|
{
|
|
/* The request seems valid... let the class implementation handle it */
|
|
|
|
stm32_dispatchrequest(priv);
|
|
handled = TRUE;
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_SETCONFIGURATION:
|
|
/* type: host-to-device; recipient = device
|
|
* value: configuration value
|
|
* index: 0;
|
|
* len: 0; data = none
|
|
*/
|
|
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), priv->ctrl.type);
|
|
if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
|
|
index.w == 0 && len.w == 0)
|
|
{
|
|
/* The request seems valid... let the class implementation handle it */
|
|
|
|
stm32_dispatchrequest(priv);
|
|
handled = TRUE;
|
|
}
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_GETINTERFACE:
|
|
/* type: device-to-host; recipient = interface
|
|
* value: 0
|
|
* index: interface;
|
|
* len: 1; data = alt interface
|
|
*/
|
|
case USB_REQ_SETINTERFACE:
|
|
/* type: host-to-device; recipient = interface
|
|
* value: alternate setting
|
|
* index: interface;
|
|
* len: 0; data = none
|
|
*/
|
|
|
|
{
|
|
/* Let the class implementation handle the request */
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type);
|
|
stm32_dispatchrequest(priv);
|
|
handled = TRUE;
|
|
}
|
|
break;
|
|
|
|
case USB_REQ_SYNCHFRAME:
|
|
/* type: device-to-host; recipient = endpoint
|
|
* value: 0
|
|
* index: endpoint;
|
|
* len: 2; data = frame number
|
|
*/
|
|
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* At this point, the request has been handled and there are three possible
|
|
* outcomes:
|
|
*
|
|
* 1. The setup request was successfully handled above and a response packet
|
|
* must be sent (may be a zero length packet).
|
|
* 2. The request was successfully handled by the class implementation. In
|
|
* case, the EP0 IN response has already been queued and the local variable
|
|
* 'handled' will be set to TRUE and devstate != DEVSTATE_STALLED;
|
|
* 3. An error was detected in either the above logic or by the class implementation
|
|
* logic. In either case, priv->state will be set DEVSTATE_STALLED
|
|
* to indicate this case.
|
|
*
|
|
* NOTE: Non-standard requests are a special case. They are handled by the
|
|
* class implementation and this function returned early above, skipping this
|
|
* logic altogether.
|
|
*/
|
|
|
|
if (priv->devstate != DEVSTATE_STALLED && !handled)
|
|
{
|
|
/* We will response. First, restrict the data length to the length
|
|
* requested in the setup packet
|
|
*/
|
|
|
|
if (nbytes > len.w)
|
|
{
|
|
nbytes = len.w;
|
|
}
|
|
|
|
/* Send the response (might be a zero-length packet) */
|
|
|
|
stm32_epwrite(priv, ep0, response.b, nbytes);
|
|
priv->devstate = DEVSTATE_IDLE;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_ep0in
|
|
****************************************************************************/
|
|
|
|
static void stm32_ep0in(struct stm32_usbdev_s *priv)
|
|
{
|
|
/* There is no longer anything in the EP0 TX packet memory */
|
|
|
|
priv->eplist[EP0].txbusy = FALSE;
|
|
|
|
/* Are we processing the completion of one packet of an outgoing request
|
|
* from the class driver?
|
|
*/
|
|
|
|
if (priv->devstate == DEVSTATE_WRREQUEST)
|
|
{
|
|
stm32_wrrequest(priv, &priv->eplist[EP0]);
|
|
}
|
|
|
|
/* No.. Are we processing the completion of a status response? */
|
|
|
|
else if (priv->devstate == DEVSTATE_IDLE)
|
|
{
|
|
/* Look at the saved SETUP command. Was it a SET ADDRESS request?
|
|
* If so, then now is the time to set the address.
|
|
*/
|
|
|
|
if (priv->ctrl.req == USB_REQ_SETADDRESS &&
|
|
(priv->ctrl.type & REQRECIPIENT_MASK) == (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE))
|
|
{
|
|
union wb_u value;
|
|
value.w = GETUINT16(priv->ctrl.value);
|
|
stm32_setdevaddr(priv, value.b[LSB]);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_ep0out
|
|
****************************************************************************/
|
|
|
|
static void stm32_ep0out(struct stm32_usbdev_s *priv)
|
|
{
|
|
struct stm32_ep_s *privep = &priv->eplist[EP0];
|
|
switch (priv->devstate)
|
|
{
|
|
case DEVSTATE_RDREQUEST: /* Write request in progress */
|
|
case DEVSTATE_IDLE: /* No transfer in progress */
|
|
stm32_rdrequest(priv, privep);
|
|
break;
|
|
|
|
default:
|
|
/* Unexpected state OR host aborted the OUT transfer before it
|
|
* completed, STALL the endpoint in either case
|
|
*/
|
|
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_ep0done
|
|
****************************************************************************/
|
|
|
|
static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16 istr)
|
|
{
|
|
uint16 epr;
|
|
|
|
/* Initialize RX and TX status. We shouldn't have to actually look at the
|
|
* status because the hardware is supposed to set the both RX and TX status
|
|
* to NAK when an EP0 SETUP occurs (of course, this might not be a setup)
|
|
*/
|
|
|
|
priv->rxstatus = USB_EPR_STATRX_NAK;
|
|
priv->txstatus = USB_EPR_STATTX_NAK;
|
|
|
|
/* Set both RX and TX status to NAK */
|
|
|
|
stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK);
|
|
stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK);
|
|
|
|
/* Check the direction bit to determine if this the completion of an EP0
|
|
* packet sent to or received from the host PC.
|
|
*/
|
|
|
|
if ((istr & USB_ISTR_DIR) == 0)
|
|
{
|
|
/* EP0 IN: device-to-host (DIR=0) */
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr);
|
|
stm32_clrepctrtx(EP0);
|
|
stm32_ep0in(priv);
|
|
}
|
|
else
|
|
{
|
|
/* EP0 OUT: host-to-device (DIR=1) */
|
|
|
|
epr = stm32_getreg(STM32_USB_EPR(EP0));
|
|
|
|
/* CTR_TX is set when an IN transaction successfully
|
|
* completes on an endpoint
|
|
*/
|
|
|
|
if ((epr & USB_EPR_CTR_TX) != 0)
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr);
|
|
stm32_clrepctrtx(EP0);
|
|
stm32_ep0in(priv);
|
|
}
|
|
|
|
/* SETUP is set by the hardware when the last completed
|
|
* transaction was a control endpoint SETUP
|
|
*/
|
|
|
|
else if ((epr & USB_EPR_SETUP) != 0)
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr);
|
|
stm32_clrepctrrx(EP0);
|
|
stm32_ep0setup(priv);
|
|
}
|
|
|
|
/* Set by the hardware when an OUT/SETUP transaction successfully
|
|
* completed on this endpoint.
|
|
*/
|
|
|
|
else if ((epr & USB_EPR_CTR_RX) != 0)
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr);
|
|
stm32_clrepctrrx(EP0);
|
|
stm32_ep0out(priv);
|
|
}
|
|
|
|
/* None of the above */
|
|
|
|
else
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr);
|
|
return; /* Does this ever happen? */
|
|
}
|
|
}
|
|
|
|
/* Make sure that the EP0 packet size is still OK (superstitious?) */
|
|
|
|
stm32_seteprxcount(EP0, STM32_EP0MAXPACKET);
|
|
|
|
/* Now figure out the new RX/TX status. Here are all possible
|
|
* consequences of the above EP0 operations:
|
|
*
|
|
* rxstatus txstatus devstate MEANING
|
|
* -------- -------- --------- ---------------------------------
|
|
* NAK NAK IDLE Nothing happened
|
|
* NAK VALID IDLE EP0 response sent from USBDEV driver
|
|
* NAK VALID WRREQUEST EP0 response sent from class driver
|
|
* NAK --- STALL Some protocol error occurred
|
|
*
|
|
* First handle the STALL condition:
|
|
*/
|
|
|
|
if (priv->devstate == DEVSTATE_STALLED)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->devstate);
|
|
priv->rxstatus = USB_EPR_STATRX_STALL;
|
|
priv->txstatus = USB_EPR_STATTX_STALL;
|
|
}
|
|
|
|
/* Was a transmission started? If so, txstatus will be VALID. The
|
|
* only special case to handle is when both are set to NAK. In that
|
|
* case, we need to for RX status to VALID in order to accept the next
|
|
* SETUP request.
|
|
*/
|
|
|
|
else if (priv->rxstatus == USB_EPR_STATRX_NAK &&
|
|
priv->txstatus == USB_EPR_STATTX_NAK)
|
|
{
|
|
priv->rxstatus = USB_EPR_STATRX_VALID;
|
|
}
|
|
|
|
/* Now set the new TX and RX status */
|
|
|
|
stm32_seteprxstatus(EP0, priv->rxstatus);
|
|
stm32_seteptxstatus(EP0, priv->txstatus);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_lptransfer
|
|
****************************************************************************/
|
|
|
|
static void stm32_lptransfer(struct stm32_usbdev_s *priv)
|
|
{
|
|
ubyte epno;
|
|
uint16 istr;
|
|
|
|
/* Stay in loop while LP interrupts are pending */
|
|
|
|
while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0)
|
|
{
|
|
stm32_putreg((uint16)~USB_ISTR_CTR, STM32_USB_ISTR);
|
|
|
|
/* Extract highest priority endpoint number */
|
|
|
|
epno = (ubyte)(istr & USB_ISTR_EPID_MASK);
|
|
|
|
/* Handle EP0 completion events */
|
|
|
|
if (epno == 0)
|
|
{
|
|
stm32_ep0done(priv, istr);
|
|
}
|
|
|
|
/* Handle other endpoint completion events */
|
|
|
|
else
|
|
{
|
|
stm32_epdone(priv, epno);
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_hpinterrupt
|
|
****************************************************************************/
|
|
|
|
static int stm32_hpinterrupt(int irq, void *context)
|
|
{
|
|
/* For now there is only one USB controller, but we will always refer to
|
|
* it using a pointer to make any future ports to multiple USB controllers
|
|
* easier.
|
|
*/
|
|
|
|
struct stm32_usbdev_s *priv = &g_usbdev;
|
|
uint16 istr;
|
|
ubyte epno;
|
|
|
|
/* High priority interrupts are only triggered by a correct transfer event
|
|
* for isochronous and double-buffer bulk transfers.
|
|
*/
|
|
|
|
istr = stm32_getreg(STM32_USB_ISTR);
|
|
usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_HPINTERRUPT), istr);
|
|
while ((istr & USB_ISTR_CTR) != 0)
|
|
{
|
|
stm32_putreg((uint16)~USB_ISTR_CTR, STM32_USB_ISTR);
|
|
|
|
/* Extract highest priority endpoint number */
|
|
|
|
epno = (ubyte)(istr & USB_ISTR_EPID_MASK);
|
|
|
|
/* And handle the completion event */
|
|
|
|
stm32_epdone(priv, epno);
|
|
|
|
/* Fetch the status again for the next time through the loop */
|
|
|
|
istr = stm32_getreg(STM32_USB_ISTR);
|
|
}
|
|
|
|
usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_HPINTERRUPT), 0);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_lpinterrupt
|
|
****************************************************************************/
|
|
|
|
static int stm32_lpinterrupt(int irq, void *context)
|
|
{
|
|
/* For now there is only one USB controller, but we will always refer to
|
|
* it using a pointer to make any future ports to multiple USB controllers
|
|
* easier.
|
|
*/
|
|
|
|
struct stm32_usbdev_s *priv = &g_usbdev;
|
|
uint16 istr = stm32_getreg(STM32_USB_ISTR);
|
|
|
|
usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_LPINTERRUPT), istr);
|
|
|
|
/* Handle Reset interrupts. When this event occurs, the peripheral is left
|
|
* in the same conditions it is left by the system reset (but with the
|
|
* USB controller enabled).
|
|
*/
|
|
|
|
if ((istr & USB_ISTR_RESET) != 0)
|
|
{
|
|
/* Wakeup interrupt received. Clear the WKUP interrupt status. The cause of
|
|
* the wakeup is indicated in the FNR register
|
|
*/
|
|
|
|
stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR);
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), stm32_getreg(STM32_USB_FNR));
|
|
|
|
/* Restore our power-up state and exit now because istr is no longer
|
|
* valid.
|
|
*/
|
|
|
|
stm32_reset(priv);
|
|
goto exit_lpinterrupt;
|
|
}
|
|
|
|
/* Handle Wakeup interrupts. This interrupt is only enable while the USB is
|
|
* suspended.
|
|
*/
|
|
|
|
if ((istr & USB_ISTR_WKUP & priv->imask) != 0)
|
|
{
|
|
/* Wakeup interrupt received. Clear the WKUP interrupt status. */
|
|
|
|
stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR);
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), 0);
|
|
|
|
/* Perform the wakeup action */
|
|
|
|
stm32_initresume(priv);
|
|
priv->rsmstate = RSMSTATE_IDLE;
|
|
|
|
/* Disable ESOF polling, disable the wakeup interrupt, and
|
|
* re-enable the suspend interrupt. Clear any pending SUSP
|
|
* interrupts.
|
|
*/
|
|
|
|
stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM|USB_CNTR_WKUPM);
|
|
stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR);
|
|
}
|
|
|
|
if ((istr & USB_ISTR_SUSP & priv->imask) != 0)
|
|
{
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0);
|
|
stm32_suspend(priv);
|
|
|
|
/* Clear of the ISTR bit must be done after setting of USB_CNTR_FSUSP */
|
|
|
|
stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR);
|
|
}
|
|
|
|
if ((istr & USB_ISTR_ESOF & priv->imask) != 0)
|
|
{
|
|
stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR);
|
|
|
|
/* Resume handling timing is made with ESOFs */
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0);
|
|
stm32_esofpoll(priv);
|
|
}
|
|
|
|
if ((istr & USB_ISTR_CTR & priv->imask) != 0)
|
|
{
|
|
/* Low priority endpoint correct transfer interrupt */
|
|
|
|
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr);
|
|
stm32_lptransfer(priv);
|
|
}
|
|
|
|
exit_lpinterrupt:
|
|
usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_LPINTERRUPT), stm32_getreg(STM32_USB_EP0R));
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_setimask
|
|
****************************************************************************/
|
|
|
|
static void
|
|
stm32_setimask(struct stm32_usbdev_s *priv, uint16 setbits, uint16 clrbits)
|
|
{
|
|
uint16 regval;
|
|
|
|
/* Adjust the interrupt mask bits in the shadow copy first */
|
|
|
|
priv->imask &= ~clrbits;
|
|
priv->imask |= setbits;
|
|
|
|
/* Then make the interrupt mask bits in the CNTR register match the shadow
|
|
* register (Hmmm... who is shadowing whom?)
|
|
*/
|
|
|
|
regval = stm32_getreg(STM32_USB_CNTR);
|
|
regval &= ~USB_CNTR_ALLINTS;
|
|
regval |= priv->imask;
|
|
stm32_putreg(regval, STM32_USB_CNTR);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Suspend/Resume Helpers
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_suspend
|
|
****************************************************************************/
|
|
|
|
static void stm32_suspend(struct stm32_usbdev_s *priv)
|
|
{
|
|
uint16 regval;
|
|
|
|
/* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP
|
|
* interrupt. Clear any pending WKUP interrupt.
|
|
*/
|
|
|
|
stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM|USB_CNTR_SUSPM);
|
|
stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR);
|
|
|
|
/* Set the FSUSP bit in the CNTR register. This activates suspend mode
|
|
* within the USB peripheral and disables further SUSP interrupts.
|
|
*/
|
|
|
|
regval = stm32_getreg(STM32_USB_CNTR);
|
|
regval |= USB_CNTR_FSUSP;
|
|
stm32_putreg(regval, STM32_USB_CNTR);
|
|
|
|
/* If we are not a self-powered device, the got to low-power mode */
|
|
|
|
if (!priv->selfpowered)
|
|
{
|
|
/* Setting LPMODE in the CNTR register removes static power
|
|
* consumption in the USB analog transceivers but keeps them
|
|
* able to detect resume activity
|
|
*/
|
|
|
|
regval = stm32_getreg(STM32_USB_CNTR);
|
|
regval |= USB_CNTR_LPMODE;
|
|
stm32_putreg(regval, STM32_USB_CNTR);
|
|
}
|
|
|
|
/* Let the board-specific logic know that we have entered the suspend
|
|
* state
|
|
*/
|
|
|
|
stm32_usbsuspend((struct usbdev_s *)priv, FALSE);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_initresume
|
|
****************************************************************************/
|
|
|
|
static void stm32_initresume(struct stm32_usbdev_s *priv)
|
|
{
|
|
uint16 regval;
|
|
|
|
/* This function is called when either (1) a WKUP interrupt is received from
|
|
* the host PC, or (2) the class device implementation calls the wakeup()
|
|
* method.
|
|
*/
|
|
|
|
/* Clear the USB low power mode (lower power mode was not set if this is
|
|
* a self-powered device. Also, low power mode is automatically cleared by
|
|
* hardware when a WKUP interrupt event occurs).
|
|
*/
|
|
|
|
regval = stm32_getreg(STM32_USB_CNTR);
|
|
regval &= (~USB_CNTR_LPMODE);
|
|
stm32_putreg(regval, STM32_USB_CNTR);
|
|
|
|
/* Restore full power -- whatever that means for this particular board */
|
|
|
|
stm32_usbsuspend((struct usbdev_s *)priv, TRUE);
|
|
|
|
/* Reset FSUSP bit and enable normal interrupt handling */
|
|
|
|
stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_esofpoll
|
|
****************************************************************************/
|
|
|
|
static void stm32_esofpoll(struct stm32_usbdev_s *priv)
|
|
{
|
|
uint16 regval;
|
|
|
|
/* Called periodically from ESOF interrupt after RSMSTATE_STARTED */
|
|
|
|
switch (priv->rsmstate)
|
|
{
|
|
/* One ESOF after internal resume requested */
|
|
|
|
case RSMSTATE_STARTED:
|
|
regval = stm32_getreg(STM32_USB_CNTR);
|
|
regval |= USB_CNTR_RESUME;
|
|
stm32_putreg(regval, STM32_USB_CNTR);
|
|
priv->rsmstate = RSMSTATE_WAITING;
|
|
priv->nesofs = 10;
|
|
break;
|
|
|
|
/* Countdown before completing the operation */
|
|
|
|
case RSMSTATE_WAITING:
|
|
priv->nesofs--;
|
|
if (priv->nesofs == 0)
|
|
{
|
|
/* Okay.. we are ready to resume normal operation */
|
|
|
|
regval = stm32_getreg(STM32_USB_CNTR);
|
|
regval &= (~USB_CNTR_RESUME);
|
|
stm32_putreg(regval, STM32_USB_CNTR);
|
|
priv->rsmstate = RSMSTATE_IDLE;
|
|
|
|
/* Disable ESOF polling, disable the SUSP interrupt, and enable
|
|
* the WKUP interrupt. Clear any pending WKUP interrupt.
|
|
*/
|
|
|
|
stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM|USB_CNTR_SUSPM);
|
|
stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR);
|
|
}
|
|
break;
|
|
|
|
case RSMSTATE_IDLE:
|
|
default:
|
|
priv->rsmstate = RSMSTATE_IDLE;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Endpoint Helpers
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_epreserve
|
|
****************************************************************************/
|
|
|
|
static inline struct stm32_ep_s *
|
|
stm32_epreserve(struct stm32_usbdev_s *priv, ubyte epset)
|
|
{
|
|
struct stm32_ep_s *privep = NULL;
|
|
irqstate_t flags;
|
|
int epndx = 0;
|
|
|
|
flags = irqsave();
|
|
epset &= priv->epavail;
|
|
if (epset)
|
|
{
|
|
/* Select the lowest bit in the set of matching, available endpoints
|
|
* (skipping EP0)
|
|
*/
|
|
|
|
for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++)
|
|
{
|
|
ubyte bit = STM32_ENDP_BIT(epndx);
|
|
if ((epset & bit) != 0)
|
|
{
|
|
/* Mark the endpoint no longer available */
|
|
|
|
priv->epavail &= ~bit;
|
|
|
|
/* And return the pointer to the standard endpoint structure */
|
|
|
|
privep = &priv->eplist[epndx];
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
irqrestore(flags);
|
|
return privep;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epunreserve
|
|
****************************************************************************/
|
|
|
|
static inline void
|
|
stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep)
|
|
{
|
|
irqstate_t flags = irqsave();
|
|
priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog));
|
|
irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epreserved
|
|
****************************************************************************/
|
|
|
|
static inline boolean
|
|
stm32_epreserved(struct stm32_usbdev_s *priv, int epno)
|
|
{
|
|
return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epallocpma
|
|
****************************************************************************/
|
|
|
|
static int stm32_epallocpma(struct stm32_usbdev_s *priv)
|
|
{
|
|
irqstate_t flags;
|
|
int bufno = ERROR;
|
|
int bufndx;
|
|
|
|
flags = irqsave();
|
|
for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++)
|
|
{
|
|
/* Check if this buffer is available */
|
|
|
|
ubyte bit = STM32_BUFFER_BIT(bufndx);
|
|
if ((priv->bufavail & bit) != 0)
|
|
{
|
|
/* Yes.. Mark the endpoint no longer available */
|
|
|
|
priv->bufavail &= ~bit;
|
|
|
|
/* And return the index of the allocated buffer */
|
|
|
|
bufno = bufndx;
|
|
break;
|
|
}
|
|
}
|
|
|
|
irqrestore(flags);
|
|
return bufno;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epfreepma
|
|
****************************************************************************/
|
|
|
|
static inline void
|
|
stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep)
|
|
{
|
|
irqstate_t flags = irqsave();
|
|
priv->epavail |= STM32_ENDP_BIT(privep->bufno);
|
|
irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Endpoint operations
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_epconfigure
|
|
****************************************************************************/
|
|
|
|
static int stm32_epconfigure(struct usbdev_ep_s *ep,
|
|
const struct usb_epdesc_s *desc,
|
|
boolean last)
|
|
{
|
|
struct stm32_ep_s *privep = (struct stm32_ep_s *)ep;
|
|
uint16 pma;
|
|
uint16 setting;
|
|
uint16 maxpacket;
|
|
ubyte epno;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!ep || !desc)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
ulldbg("ERROR: ep=%p desc=%p\n");
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
/* Get the unadorned endpoint address */
|
|
|
|
epno = USB_EPNO(desc->addr);
|
|
usbtrace(TRACE_EPCONFIGURE, (uint16)epno);
|
|
DEBUGASSERT(epno == USB_EPNO(ep->eplog));
|
|
|
|
/* Set the requested type */
|
|
|
|
switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK)
|
|
{
|
|
case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */
|
|
setting = USB_EPR_EPTYPE_INTERRUPT;
|
|
break;
|
|
|
|
case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */
|
|
setting = USB_EPR_EPTYPE_BULK;
|
|
break;
|
|
|
|
case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */
|
|
#warning "REVISIT: Need to review isochronous EP setup"
|
|
setting = USB_EPR_EPTYPE_ISOC;
|
|
break;
|
|
|
|
case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */
|
|
setting = USB_EPR_EPTYPE_CONTROL;
|
|
break;
|
|
|
|
default:
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16)desc->type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
stm32_seteptype(epno, setting);
|
|
|
|
/* Get the address of the PMA buffer allocated for this endpoint */
|
|
|
|
#warning "REVISIT: Should configure BULK EPs using double buffer feature"
|
|
pma = STM32_BUFNO2BUF(privep->bufno);
|
|
|
|
/* Get the maxpacket size of the endpoint. */
|
|
|
|
maxpacket = GETUINT16(desc->mxpacketsize);
|
|
DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE);
|
|
ep->maxpacket = maxpacket;
|
|
|
|
/* Get the subset matching the requested direction */
|
|
|
|
if (USB_ISEPIN(desc->addr))
|
|
{
|
|
/* The full, logical EP number includes direction (which is zero
|
|
* for IN endpoints.
|
|
*/
|
|
|
|
ep->eplog = USB_EPIN(epno);
|
|
|
|
/* Set up TX; disable RX */
|
|
|
|
stm32_seteptxaddr(epno, pma);
|
|
stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK);
|
|
stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS);
|
|
}
|
|
else
|
|
{
|
|
/* The full, logical EP number includes direction */
|
|
|
|
ep->eplog = USB_EPOUT(epno);
|
|
|
|
/* Set up RX; disable TX */
|
|
|
|
stm32_seteprxaddr(epno, pma);
|
|
stm32_seteprxcount(epno, maxpacket);
|
|
stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID);
|
|
stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS);
|
|
}
|
|
|
|
stm32_dumpep(epno);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epdisable
|
|
****************************************************************************/
|
|
|
|
static int stm32_epdisable(struct usbdev_ep_s *ep)
|
|
{
|
|
struct stm32_ep_s *privep = (struct stm32_ep_s *)ep;
|
|
irqstate_t flags;
|
|
ubyte epno;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!ep)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
ulldbg("ERROR: ep=%p\n", ep);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
epno = USB_EPNO(ep->eplog);
|
|
usbtrace(TRACE_EPDISABLE, epno);
|
|
|
|
/* Cancel any ongoing activity */
|
|
|
|
flags = irqsave();
|
|
stm32_cancelrequests(privep);
|
|
|
|
/* Disable TX; disable RX */
|
|
|
|
stm32_seteprxcount(epno, 0);
|
|
stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS);
|
|
stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS);
|
|
|
|
irqrestore(flags);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epallocreq
|
|
****************************************************************************/
|
|
|
|
static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep)
|
|
{
|
|
struct stm32_req_s *privreq;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!ep)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return NULL;
|
|
}
|
|
#endif
|
|
usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog));
|
|
|
|
privreq = (struct stm32_req_s *)malloc(sizeof(struct stm32_req_s));
|
|
if (!privreq)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0);
|
|
return NULL;
|
|
}
|
|
|
|
memset(privreq, 0, sizeof(struct stm32_req_s));
|
|
return &privreq->req;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epfreereq
|
|
****************************************************************************/
|
|
|
|
static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
|
|
{
|
|
struct stm32_req_s *privreq = (struct stm32_req_s*)req;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!ep || !req)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return;
|
|
}
|
|
#endif
|
|
usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog));
|
|
|
|
free(privreq);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epsubmit
|
|
****************************************************************************/
|
|
|
|
static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
|
|
{
|
|
struct stm32_req_s *privreq = (struct stm32_req_s *)req;
|
|
struct stm32_ep_s *privep = (struct stm32_ep_s *)ep;
|
|
struct stm32_usbdev_s *priv;
|
|
irqstate_t flags;
|
|
int ret = OK;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!req || !req->callback || !req->buf || !ep)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
ulldbg("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
|
|
priv = privep->dev;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!priv->driver)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
|
|
ulldbg("ERROR: driver=%p\n", priv->driver);
|
|
return -ESHUTDOWN;
|
|
}
|
|
#endif
|
|
|
|
/* Handle the request from the class driver */
|
|
|
|
req->result = -EINPROGRESS;
|
|
req->xfrd = 0;
|
|
flags = irqsave();
|
|
|
|
/* If we are stalled, then drop all requests on the floor */
|
|
|
|
if (privep->stalled)
|
|
{
|
|
stm32_abortrequest(privep, privreq, -EBUSY);
|
|
ulldbg("ERROR: stalled\n");
|
|
ret = -EBUSY;
|
|
}
|
|
|
|
/* Handle IN (device-to-host) requests. NOTE: If the class device is
|
|
* using the bi-directional EP0, then we assume that they intend the EP0
|
|
* IN functionality.
|
|
*/
|
|
|
|
else if (USB_ISEPIN(ep->eplog) || USB_EPNO(ep->eplog) == EP0)
|
|
{
|
|
/* Add the new request to the request queue for the IN endpoint */
|
|
|
|
stm32_rqenqueue(privep, privreq);
|
|
usbtrace(TRACE_INREQQUEUED(USB_EPNO(ep->eplog)), req->len);
|
|
|
|
/* If the IN endpoint FIFO is available, then transfer the data now */
|
|
|
|
if (!privep->txbusy)
|
|
{
|
|
ret = stm32_wrrequest(priv, privep);
|
|
}
|
|
}
|
|
|
|
/* Handle OUT (host-to-device) requests */
|
|
|
|
else
|
|
{
|
|
/* Add the new request to the request queue for the OUT endpoint */
|
|
|
|
privep->txnullpkt = 0;
|
|
stm32_rqenqueue(privep, privreq);
|
|
usbtrace(TRACE_OUTREQQUEUED(USB_EPNO(ep->eplog)), req->len);
|
|
|
|
/* This there a incoming data pending the availability of a request? */
|
|
|
|
if (priv->rxpending)
|
|
{
|
|
ret = stm32_rdrequest(priv, privep);
|
|
priv->rxpending = 0;
|
|
}
|
|
}
|
|
|
|
irqrestore(flags);
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epcancel
|
|
****************************************************************************/
|
|
|
|
static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
|
|
{
|
|
struct stm32_ep_s *privep = (struct stm32_ep_s *)ep;
|
|
struct stm32_usbdev_s *priv;
|
|
irqstate_t flags;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!ep || !req)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog));
|
|
priv = privep->dev;
|
|
|
|
flags = irqsave();
|
|
stm32_cancelrequests(privep);
|
|
irqrestore(flags);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_epstall
|
|
****************************************************************************/
|
|
|
|
static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume)
|
|
{
|
|
struct stm32_ep_s *privep;
|
|
struct stm32_usbdev_s *priv;
|
|
ubyte epno = USB_EPNO(ep->eplog);
|
|
uint16 status;
|
|
irqstate_t flags;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!ep)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
privep = (struct stm32_ep_s *)ep;
|
|
priv = (struct stm32_usbdev_s *)privep->dev;
|
|
epno = USB_EPNO(ep->eplog);
|
|
|
|
/* STALL or RESUME the endpoint */
|
|
|
|
flags = irqsave();
|
|
usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog));
|
|
|
|
/* Get status of the endpoint; stall the request if the endpoint is
|
|
* disabled
|
|
*/
|
|
|
|
if (USB_ISEPIN(ep->eplog))
|
|
{
|
|
status = stm32_geteptxstatus(epno);
|
|
}
|
|
else
|
|
{
|
|
status = stm32_geteprxstatus(epno);
|
|
}
|
|
|
|
if (status == 0)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0);
|
|
priv->devstate = DEVSTATE_STALLED;
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Handle the resume condition */
|
|
|
|
if (resume)
|
|
{
|
|
/* Resuming a stalled endpoint */
|
|
|
|
usbtrace(TRACE_EPRESUME, epno);
|
|
privep->stalled = FALSE;
|
|
|
|
if (USB_ISEPIN(ep->eplog))
|
|
{
|
|
/* IN endpoint */
|
|
|
|
if (stm32_eptxstalled(epno))
|
|
{
|
|
stm32_clrtxdtog(epno);
|
|
|
|
/* Restart any queued write requests */
|
|
|
|
if (!stm32_rqempty(privep))
|
|
{
|
|
(void)stm32_wrrequest(priv, privep);
|
|
stm32_seteptxstatus(epno, USB_EPR_STATTX_VALID);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* OUT endpoint */
|
|
|
|
if (stm32_eprxstalled(epno))
|
|
{
|
|
if (epno == EP0)
|
|
{
|
|
/* After clear the STALL, enable the default endpoint receiver */
|
|
|
|
stm32_seteprxcount(epno, ep->maxpacket);
|
|
}
|
|
else
|
|
{
|
|
stm32_clrrxdtog(epno);
|
|
}
|
|
stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Handle the stall condition */
|
|
|
|
else
|
|
{
|
|
usbtrace(TRACE_EPSTALL, epno);
|
|
privep->stalled = TRUE;
|
|
|
|
if (USB_ISEPIN(ep->eplog))
|
|
{
|
|
/* IN endpoint */
|
|
|
|
stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL);
|
|
}
|
|
else
|
|
{
|
|
/* OUT endpoint */
|
|
|
|
stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL);
|
|
}
|
|
}
|
|
|
|
irqrestore(flags);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Device Controller Operations
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: stm32_allocep
|
|
****************************************************************************/
|
|
|
|
static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, ubyte epno,
|
|
boolean in, ubyte eptype)
|
|
{
|
|
struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev;
|
|
struct stm32_ep_s *privep = NULL;
|
|
ubyte epset = STM32_ENDP_ALLSET;
|
|
int bufno;
|
|
|
|
usbtrace(TRACE_DEVALLOCEP, (uint16)epno);
|
|
#ifdef CONFIG_DEBUG
|
|
if (!dev)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
/* Ignore any direction bits in the logical address */
|
|
|
|
epno = USB_EPNO(epno);
|
|
|
|
/* A logical address of 0 means that any endpoint will do */
|
|
|
|
if (epno > 0)
|
|
{
|
|
/* Otherwise, we will return the endpoint structure only for the requested
|
|
* 'logical' endpoint. All of the other checks will still be performed.
|
|
*
|
|
* First, verify that the logical endpoint is in the range supported by
|
|
* by the hardware.
|
|
*/
|
|
|
|
if (epno >= STM32_NENDPOINTS)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16)epno);
|
|
return NULL;
|
|
}
|
|
|
|
/* Convert the logical address to a physical OUT endpoint address and
|
|
* remove all of the candidate endpoints from the bitset except for the
|
|
* the IN/OUT pair for this logical address.
|
|
*/
|
|
|
|
epset = STM32_ENDP_BIT(epno);
|
|
}
|
|
|
|
/* Check if the selected endpoint number is available */
|
|
|
|
privep = stm32_epreserve(priv, epset);
|
|
if (!privep)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16)epset);
|
|
goto errout;
|
|
}
|
|
epno = USB_EPNO(privep->ep.eplog);
|
|
|
|
/* Allocate a PMA buffer for this endpoint */
|
|
|
|
#warning "REVISIT: Should configure BULK EPs using double buffer feature"
|
|
bufno = stm32_epallocpma(priv);
|
|
if (bufno < 0)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0);
|
|
goto errout_with_ep;
|
|
}
|
|
privep->bufno = (ubyte)bufno;
|
|
return &privep->ep;
|
|
|
|
errout_with_ep:
|
|
stm32_epunreserve(priv, privep);
|
|
errout:
|
|
return NULL;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_freeep
|
|
****************************************************************************/
|
|
|
|
static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
|
|
{
|
|
struct stm32_usbdev_s *priv;
|
|
struct stm32_ep_s *privep;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!dev || !ep)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return;
|
|
}
|
|
#endif
|
|
priv = (struct stm32_usbdev_s *)dev;
|
|
privep = (struct stm32_ep_s *)ep;
|
|
usbtrace(TRACE_DEVFREEEP, (uint16)USB_EPNO(ep->eplog));
|
|
|
|
if (priv && privep)
|
|
{
|
|
/* Free the PMA buffer assigned to this endpoint */
|
|
|
|
stm32_epfreepma(priv, privep);
|
|
|
|
/* Mark the endpoint as available */
|
|
|
|
stm32_epunreserve(priv, privep);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_getframe
|
|
****************************************************************************/
|
|
|
|
static int stm32_getframe(struct usbdev_s *dev)
|
|
{
|
|
uint16 fnr;
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!dev)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
/* Return the last frame number detected by the hardware */
|
|
|
|
fnr = stm32_getreg(STM32_USB_FNR);
|
|
usbtrace(TRACE_DEVGETFRAME, fnr);
|
|
return (fnr & USB_FNR_FN_MASK);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_wakeup
|
|
****************************************************************************/
|
|
|
|
static int stm32_wakeup(struct usbdev_s *dev)
|
|
{
|
|
struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev;
|
|
irqstate_t flags;
|
|
|
|
usbtrace(TRACE_DEVWAKEUP, 0);
|
|
#ifdef CONFIG_DEBUG
|
|
if (!dev)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
/* Start the resume sequence. The actual resume steps will be driven
|
|
* by the ESOF interrupt.
|
|
*/
|
|
|
|
flags = irqsave();
|
|
stm32_initresume(priv);
|
|
priv->rsmstate = RSMSTATE_STARTED;
|
|
|
|
/* Disable the SUSP interrupt (until we are fully resumed), disable
|
|
* the WKUP interrupt (we are already waking up), and enable the
|
|
* ESOF interrupt that will drive the resume operations. Clear any
|
|
* pending ESOF interrupt.
|
|
*/
|
|
|
|
stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM|USB_CNTR_SUSPM);
|
|
stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR);
|
|
irqrestore(flags);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_selfpowered
|
|
****************************************************************************/
|
|
|
|
static int stm32_selfpowered(struct usbdev_s *dev, boolean selfpowered)
|
|
{
|
|
struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev;
|
|
|
|
usbtrace(TRACE_DEVSELFPOWERED, (uint16)selfpowered);
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!dev)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -ENODEV;
|
|
}
|
|
#endif
|
|
|
|
priv->selfpowered = selfpowered;
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Initialization/Reset
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_reset
|
|
****************************************************************************/
|
|
|
|
static void stm32_reset(struct stm32_usbdev_s *priv)
|
|
{
|
|
int epno;
|
|
|
|
/* Put the USB controller in reset, disable all interrupts */
|
|
|
|
stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR);
|
|
|
|
/* Reset the device state structure */
|
|
|
|
priv->devstate = DEVSTATE_IDLE;
|
|
priv->rsmstate = RSMSTATE_IDLE;
|
|
priv->rxpending = FALSE;
|
|
|
|
/* Reset endpoints */
|
|
|
|
for (epno = 0; epno < STM32_NENDPOINTS; epno++)
|
|
{
|
|
struct stm32_ep_s *privep = &priv->eplist[epno];
|
|
|
|
/* Cancel any queue requests */
|
|
|
|
stm32_cancelrequests(privep);
|
|
|
|
/* Reset endpoint status */
|
|
|
|
privep->stalled = FALSE;
|
|
privep->halted = FALSE;
|
|
privep->txbusy = FALSE;
|
|
privep->txnullpkt = FALSE;
|
|
}
|
|
|
|
/* Re-configure the USB controller in its initial, unconnected state */
|
|
|
|
stm32_hwreset(priv);
|
|
priv->usbdev.speed = USB_SPEED_FULL;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_hwreset
|
|
****************************************************************************/
|
|
|
|
static void stm32_hwreset(struct stm32_usbdev_s *priv)
|
|
{
|
|
/* Put the USB controller into reset, clear all interrupt enables */
|
|
|
|
stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR);
|
|
|
|
/* Disable interrupts (and perhaps take the USB controller out of reset) */
|
|
|
|
priv->imask = 0;
|
|
stm32_putreg(priv->imask, STM32_USB_CNTR);
|
|
|
|
/* Set the STM32 BTABLE address */
|
|
|
|
stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE);
|
|
|
|
/* Initialize EP0 */
|
|
|
|
stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL);
|
|
stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK);
|
|
stm32_seteprxaddr(EP0, STM32_EP0_RXADDR);
|
|
stm32_seteprxcount(EP0, STM32_EP0MAXPACKET);
|
|
stm32_seteptxaddr(EP0, STM32_EP0_TXADDR);
|
|
stm32_clrstatusout(EP0);
|
|
stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID);
|
|
|
|
/* Set the device to respond on default address */
|
|
|
|
stm32_setdevaddr(priv, 0);
|
|
|
|
/* Clear any pending interrupts */
|
|
|
|
stm32_putreg(0, STM32_USB_ISTR);
|
|
|
|
/* Enable interrupts at the USB controller */
|
|
|
|
stm32_setimask(priv, STM32_CNTR_SETUP, (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP));
|
|
stm32_dumpep(EP0);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
/****************************************************************************
|
|
* Name: up_usbinitialize
|
|
* Description:
|
|
* Initialize the USB driver
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void up_usbinitialize(void)
|
|
{
|
|
/* For now there is only one USB controller, but we will always refer to
|
|
* it using a pointer to make any future ports to multiple USB controllers
|
|
* easier.
|
|
*/
|
|
|
|
struct stm32_usbdev_s *priv = &g_usbdev;
|
|
int epno;
|
|
|
|
usbtrace(TRACE_DEVINIT, 0);
|
|
stm32_checksetup();
|
|
|
|
/* Power the USB controller, put the USB controller into reset, disable
|
|
* all USB interrupts
|
|
*/
|
|
|
|
stm32_putreg(USB_CNTR_FRES|USB_CNTR_PDWN, STM32_USB_CNTR);
|
|
|
|
/* Disconnect the device / disable the pull-up. We don't want the
|
|
* host to enumerate us until the class driver is registered.
|
|
*/
|
|
|
|
stm32_usbpullup(&priv->usbdev, FALSE);
|
|
|
|
/* Initialize the device state structure. NOTE: many fields
|
|
* have the initial value of zero and, hence, are not explicitly
|
|
* initialized here.
|
|
*/
|
|
|
|
memset(priv, 0, sizeof(struct stm32_usbdev_s));
|
|
priv->usbdev.ops = &g_devops;
|
|
priv->usbdev.ep0 = &priv->eplist[EP0].ep;
|
|
priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0);
|
|
priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0;
|
|
|
|
/* Initialize the endpoint list */
|
|
|
|
for (epno = 0; epno < STM32_NENDPOINTS; epno++)
|
|
{
|
|
/* Set endpoint operations, reference to driver structure (not
|
|
* really necessary because there is only one controller), and
|
|
* the (physical) endpoint number which is just the index to the
|
|
* endpoint.
|
|
*/
|
|
|
|
priv->eplist[epno].ep.ops = &g_epops;
|
|
priv->eplist[epno].dev = priv;
|
|
priv->eplist[epno].ep.eplog = epno;
|
|
|
|
/* We will use a fixed maxpacket size for all endpoints (perhaps
|
|
* ISOC endpoints could have larger maxpacket???). A smaller
|
|
* packet size can be selected when the endpoint is configured.
|
|
*/
|
|
|
|
priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE;
|
|
}
|
|
|
|
/* Select a smaller endpoint size for EP0 */
|
|
|
|
#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE
|
|
priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET;
|
|
#endif
|
|
/* Configure the USB controller. USB uses the following GPIO pins:
|
|
*
|
|
* PA9 - VBUS
|
|
* PA10 - ID
|
|
* PA11 - DM
|
|
* PA12 - DP
|
|
*
|
|
* "As soon as the USB is enabled, these pins [DM and DP] are connected to
|
|
* the USB internal transceiver automatically."
|
|
*/
|
|
|
|
/* Power up the USB controller, holding it in reset. There is a delay of
|
|
* about 1uS after applying power before the USB will behave predictably.
|
|
* A 5MS delay is more than enough. NOTE that we leave the USB controller
|
|
* in the reset state; the hardware will not be initialized until the
|
|
* class driver has been bound.
|
|
*/
|
|
|
|
stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR);
|
|
up_mdelay(5);
|
|
|
|
/* Attach USB controller interrupt handlers. The hardware will not be
|
|
* initialized and interrupts will not be enabled until the class device
|
|
* driver is bound. Getting the IRQs here only makes sure that we have
|
|
* them when we need them later.
|
|
*/
|
|
|
|
if (irq_attach(STM32_IRQ_USBHPCANTX, stm32_hpinterrupt) != 0)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION),
|
|
(uint16)STM32_IRQ_USBHPCANTX);
|
|
goto errout;
|
|
}
|
|
|
|
if (irq_attach(STM32_IRQ_USBLPCANRX0, stm32_lpinterrupt) != 0)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION),
|
|
(uint16)STM32_IRQ_USBLPCANRX0);
|
|
goto errout;
|
|
}
|
|
return;
|
|
|
|
errout:
|
|
up_usbuninitialize();
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_usbuninitialize
|
|
* Description:
|
|
* Initialize the USB driver
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void up_usbuninitialize(void)
|
|
{
|
|
/* For now there is only one USB controller, but we will always refer to
|
|
* it using a pointer to make any future ports to multiple USB controllers
|
|
* easier.
|
|
*/
|
|
|
|
struct stm32_usbdev_s *priv = &g_usbdev;
|
|
uint16 regval;
|
|
irqstate_t flags;
|
|
|
|
usbtrace(TRACE_DEVUNINIT, 0);
|
|
|
|
if (priv->driver)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0);
|
|
usbdev_unregister(priv->driver);
|
|
}
|
|
|
|
flags = irqsave();
|
|
priv->usbdev.speed = USB_SPEED_UNKNOWN;
|
|
|
|
/* Disable and detach IRQs */
|
|
|
|
up_disable_irq(STM32_IRQ_USBHPCANTX);
|
|
up_disable_irq(STM32_IRQ_USBLPCANRX0);
|
|
irq_detach(STM32_IRQ_USBHPCANTX);
|
|
irq_detach(STM32_IRQ_USBLPCANRX0);
|
|
|
|
/* Disable all interrupts and force the USB controller into reset */
|
|
|
|
stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR);
|
|
|
|
/* Clear any pending interrupts */
|
|
|
|
stm32_putreg(0, STM32_USB_ISTR);
|
|
|
|
/* Disconnect the device / disable the pull-up */
|
|
|
|
stm32_usbpullup(&priv->usbdev, FALSE);
|
|
|
|
/* Power down the USB controller */
|
|
|
|
stm32_putreg(USB_CNTR_FRES|USB_CNTR_PDWN, STM32_USB_CNTR);
|
|
irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: usbdev_register
|
|
*
|
|
* Description:
|
|
* Register a USB device class driver. The class driver's bind() method will be
|
|
* called to bind it to a USB device driver.
|
|
*
|
|
****************************************************************************/
|
|
|
|
int usbdev_register(struct usbdevclass_driver_s *driver)
|
|
{
|
|
/* For now there is only one USB controller, but we will always refer to
|
|
* it using a pointer to make any future ports to multiple USB controllers
|
|
* easier.
|
|
*/
|
|
|
|
struct stm32_usbdev_s *priv = &g_usbdev;
|
|
int ret;
|
|
|
|
usbtrace(TRACE_DEVREGISTER, 0);
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
|
|
!driver->ops->disconnect || !driver->ops->setup)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (priv->driver)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0);
|
|
return -EBUSY;
|
|
}
|
|
#endif
|
|
|
|
/* First hook up the driver */
|
|
|
|
priv->driver = driver;
|
|
|
|
/* Then bind the class driver */
|
|
|
|
ret = CLASS_BIND(driver, &priv->usbdev);
|
|
if (ret)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16)-ret);
|
|
priv->driver = NULL;
|
|
}
|
|
else
|
|
{
|
|
/* Setup the USB controller -- enabling interrupts at the USB controller */
|
|
|
|
stm32_hwreset(priv);
|
|
|
|
/* Enable USB controller interrupts at the NVIC */
|
|
|
|
up_enable_irq(STM32_IRQ_USBHPCANTX);
|
|
up_enable_irq(STM32_IRQ_USBLPCANRX0);
|
|
|
|
/* Set the interrrupt priority */
|
|
|
|
up_prioritize_irq(STM32_IRQ_USBHPCANTX, CONFIG_USB_PRI);
|
|
up_prioritize_irq(STM32_IRQ_USBLPCANRX0, CONFIG_USB_PRI);
|
|
|
|
/* Enable pull-up to connect the device. The host should enumerate us
|
|
* some time after this
|
|
*/
|
|
|
|
stm32_usbpullup(&priv->usbdev, TRUE);
|
|
priv->usbdev.speed = USB_SPEED_FULL;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: usbdev_unregister
|
|
*
|
|
* Description:
|
|
* Un-register usbdev class driver.If the USB device is connected to a USB host,
|
|
* it will first disconnect(). The driver is also requested to unbind() and clean
|
|
* up any device state, before this procedure finally returns.
|
|
*
|
|
****************************************************************************/
|
|
|
|
int usbdev_unregister(struct usbdevclass_driver_s *driver)
|
|
{
|
|
/* For now there is only one USB controller, but we will always refer to
|
|
* it using a pointer to make any future ports to multiple USB controllers
|
|
* easier.
|
|
*/
|
|
|
|
struct stm32_usbdev_s *priv = &g_usbdev;
|
|
usbtrace(TRACE_DEVUNREGISTER, 0);
|
|
|
|
#ifdef CONFIG_DEBUG
|
|
if (driver != priv->driver)
|
|
{
|
|
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
/* Unbind the class driver */
|
|
|
|
CLASS_UNBIND(driver, &priv->usbdev);
|
|
|
|
/* Disable USB controller interrupts */
|
|
|
|
up_disable_irq(STM32_IRQ_USBHPCANTX);
|
|
up_disable_irq(STM32_IRQ_USBLPCANRX0);
|
|
|
|
/* Unhook the driver */
|
|
|
|
priv->driver = NULL;
|
|
return OK;
|
|
}
|
|
|
|
#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */
|