Eero Nurkkala f5cdfa73dc risc-v/mpfs: clear L2 before use ... SiFive document: "ECC Error Handling Guide" states: "Any SRAM block or cache memory containing ECC functionality needs to be initialized prior to use. ECC will correct defective bits based on memory contents, so if memory is not first initialized to a known state, then ECC will not operate as expected. It is recommended to use a DMA, if available, to write the entire SRAM or cache to zeros prior to enabling ECC reporting. If no DMA is present, use store instructions issued from the processor." Clean the cache at this early stage so no ECC errors will be flooding later. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>		2023-09-01 19:28:54 +08:00
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configs	riscv/mpfs: Set hart2 default entrypoint to -1 like the others	2023-07-26 19:58:05 -03:00
include	arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training	2023-08-17 17:50:37 +08:00
scripts	risc-v/mpfs: clear L2 before use	2023-09-01 19:28:54 +08:00
src	build: Replace "$(shell $(INCDIR) $(CC) ...)" with $(INCDIR_PREFIX)	2023-06-23 00:11:25 +03:00
Kconfig