Huang Qi f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler ...

FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

2022-04-13 18:33:36 +08:00

..

include

RISC-V: Combine 3 variables that depend on CPU amount into one

2022-04-12 01:59:35 +08:00

src

arch/risc-v: Correct format of 32-bit insn in misaligned handler

2022-04-13 18:33:36 +08:00

Kconfig

arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa

2022-04-12 21:01:14 +03:00