469d018967
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4851 42af7a65-404d-4744-a932-0658087f49c3
274 lines
16 KiB
C
274 lines
16 KiB
C
/****************************************************************************
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* arch/mips/include/pic32mx/irq_5xx6xx7xx.h
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*
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
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#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Interrupt vector numbers. These should be used to attach to interrupts
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* and to change interrupt priorities.
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*/
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#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
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#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
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#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
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#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
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#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
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#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
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#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
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#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
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#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
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#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
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#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
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#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
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#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
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#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
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#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
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#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
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#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
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#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
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#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
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#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
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#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
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#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
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#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
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#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
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#define PIC32MX_IRQ_VEC24 24 /* Vector: 24, UART1, SPI3, I2C3 */
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# define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
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# define PIC32MX_IRQ_SPI3 24 /* Vector: 24, SPI3 */
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# define PIC32MX_IRQ_I2C3 24 /* Vector: 24, I2C3 */
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#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
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#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
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#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
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#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
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#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
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#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
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#define PIC32MX_IRQ_VEC31 31 /* Vector: 31, UART3, SPI2, I2C4 */
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# define PIC32MX_IRQ_U3 31 /* Vector: 31, UART3 */
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# define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
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# define PIC32MX_IRQ_I2C4 31 /* Vector: 31, I2C4 */
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#define PIC32MX_IRQ_VEC31 32 /* Vector: 32, UART2, SPI4, I2C5 */
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# define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
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# define PIC32MX_IRQ_SPI4 32 /* Vector: 32, SPI4 */
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# define PIC32MX_IRQ_I2C5 32 /* Vector: 32, I2C5 */
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#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
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#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
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#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
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#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
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#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
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#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
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#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
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#define PIC32MX_IRQ_DMA4 40 /* Vector: 40, DMA Channel 3 */
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#define PIC32MX_IRQ_DMA5 41 /* Vector: 41, DMA Channel 3 */
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#define PIC32MX_IRQ_DMA6 42 /* Vector: 42, DMA Channel 3 */
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#define PIC32MX_IRQ_DMA7 43 /* Vector: 43, DMA Channel 3 */
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#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
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#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB Interrupt */
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#define PIC32MX_IRQ_CAN1 46 /* Vector: 46, Control Area Network 1 */
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#define PIC32MX_IRQ_CAN2 47 /* Vector: 47, Control Area Network 2 */
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#define PIC32MX_IRQ_ETH 48 /* Vector: 48, Ethernet interrupt */
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#define PIC32MX_IRQ_U4 49 /* Vector: 49, UART4 */
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#define PIC32MX_IRQ_U6 50 /* Vector: 50, UART6 */
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#define PIC32MX_IRQ_U5 51 /* Vector: 51, UART5 */
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#define PIC32MX_IRQ_BAD 52 /* Not a real IRQ number */
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#define NR_IRQS 52
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/* Interrupt numbers. These should be used for enabling and disabling
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* interrupt sources. Note that there are more interrupt sources than
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* interrupt vectors and interrupt priorities. An offset of 128 is
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* used so that there is no overlap with the IRQ numbers and to avoid
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* errors due to misuse.
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*/
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#define PIC32MX_IRQSRC0_FIRST (128+0)
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#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
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#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
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#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
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#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
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#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
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#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
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#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
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#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
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#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
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#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
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#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
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#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
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#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
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#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
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#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
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#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
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#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
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#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
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#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
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#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
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#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
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#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
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#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
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#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 Fault */
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#define PIC32MX_IRQSRC_SPI1RX (128+24) /* Vector: 23, " " Receive done */
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#define PIC32MX_IRQSRC_SPI1TX (128+25) /* Vector: 23, " " Transfer done */
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#define PIC32MX_IRQSRC_26 (128+26) /* Vector: 24, UART1, SPI3, I2C3 */
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# define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 Error */
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# define PIC32MX_IRQSRC_SPI3E (128+26) /* Vector: 24, SPI3 Fault */
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# define PIC32MX_IRQSRC_I2C3B (128+26) /* Vector: 24, I2C3 Bus collision event */
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#define PIC32MX_IRQSRC_27 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
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# define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, UART1 Receiver */
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# define PIC32MX_IRQSRC_SPI3RX (128+27) /* Vector: 24, SPI3 Receive done */
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# define PIC32MX_IRQSRC_I2C3S (128+27) /* Vector: 24, I2C3 Slave event */
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#define PIC32MX_IRQSRC_28 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
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# define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, UART1 Transmitter */
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# define PIC32MX_IRQSRC_SPI3TX (128+28) /* Vector: 24, SPI3 Transfer done */
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# define PIC32MX_IRQSRC_I2C3M (128+28) /* Vector: 24, I2C3 Master event */
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#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 Bus collision event*/
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#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " Slave event */
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#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " Master event */
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#define PIC32MX_IRQSRC0_LAST (128+31)
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#define PIC32MX_IRQSRC1_FIRST (128+32)
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#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
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#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
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#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
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#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
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#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
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#define PIC32MX_IRQSRC_37 (128+37) /* Vector: 31, UART3, SPI2, I2C4 */
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# define PIC32MX_IRQSRC_U3E (128+37) /* Vector: 31, UART3 Error */
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# define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 Fault */
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# define PIC32MX_IRQSRC_I2C4B (128+37) /* Vector: 31, I2C4 Bus collision event */
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#define PIC32MX_IRQSRC_38 (128+38) /* Vector: 31, UART3, SPI2, I2C4 */
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# define PIC32MX_IRQSRC_U3RX (128+38) /* Vector: 31, UART3 Receiver */
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# define PIC32MX_IRQSRC_SPI2RX (128+38) /* Vector: 31, SPI2 Receive done */
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# define PIC32MX_IRQSRC_I2C4S (128+38) /* Vector: 31, I2C4 Slave event */
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#define PIC32MX_IRQSRC_39 (128+39) /* Vector: 31, UART3, SPI2, I2C4 */
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# define PIC32MX_IRQSRC_U3TX (128+39) /* Vector: 31, UART3 Transmitter */
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# define PIC32MX_IRQSRC_SPI2TX (128+39) /* Vector: 31, SPI2 Transfer done */
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# define PIC32MX_IRQSRC_I2C4M (128+39) /* Vector: 31, I2C4 Master event */
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#define PIC32MX_IRQSRC_40 (128+40) /* Vector: 32, UART2, SPI4, I2C5 */
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# define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 Error */
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# define PIC32MX_IRQSRC_SPI4E (128+40) /* Vector: 32, SPI4 Fault */
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# define PIC32MX_IRQSRC_I2C5B (128+40) /* Vector: 32, I2C5 Bus collision event */
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#define PIC32MX_IRQSRC_41 (128+41) /* Vector: 32, UART2, SPI4, I2C5 */
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# define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, UART2 Receiver */
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# define PIC32MX_IRQSRC_SPI4RX (128+41) /* Vector: 32, SPI4 Receive done */
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# define PIC32MX_IRQSRC_I2C5S (128+41) /* Vector: 32, I2C5 Slave event */
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#define PIC32MX_IRQSRC_42 (128+42) /* Vector: 32, UART2, SPI4, I2C5 */
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# define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, UART2 Transmitter */
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# define PIC32MX_IRQSRC_SPI4TX (128+42) /* Vector: 32, SPI4 Transfer done */
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# define PIC32MX_IRQSRC_I2C5M (128+42) /* Vector: 32, I2C5 Master event */
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#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 Bus collision event */
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#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " Slave event */
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#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " Master event */
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#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
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#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
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#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
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#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
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#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
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#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
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#define PIC32MX_IRQSRC_DMA4 (128+52) /* Vector: 40, DMA Channel 3 */
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#define PIC32MX_IRQSRC_DMA5 (128+53) /* Vector: 41, DMA Channel 3 */
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#define PIC32MX_IRQSRC_DMA6 (128+54) /* Vector: 42, DMA Channel 3 */
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#define PIC32MX_IRQSRC_DMA7 (128+55) /* Vector: 43, DMA Channel 3 */
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#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
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#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB Interrupt */
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#define PIC32MX_IRQSRC_CAN1 (128+58) /* Vector: 46, Control Area Network 1 */
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#define PIC32MX_IRQSRC_CAN2 (128+59) /* Vector: 47, Control Area Network 2 */
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#define PIC32MX_IRQSRC_ETH (128+60) /* Vector: 48, Ethernet interrupt */
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#define PIC32MX_IRQSRC_IC1E (128+61) /* Vector: 5, Input capture 1 error */
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#define PIC32MX_IRQSRC_IC2E (128+62) /* Vector: 9, Input capture 1 error */
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#define PIC32MX_IRQSRC_IC3E (128+63) /* Vector: 13, Input capture 1 error */
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#define PIC32MX_IRQSRC1_LAST (128+63)
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#define PIC32MX_IRQSRC2_FIRST (128+64)
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#define PIC32MX_IRQSRC_IC4E (128+64) /* Vector: 17, Input capture 1 error */
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#define PIC32MX_IRQSRC_IC5E (128+65) /* Vector: 21, Input capture 1 error */
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#define PIC32MX_IRQSRC_PMPE (128+66) /* Vector: 28, Parallel master port error */
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#define PIC32MX_IRQSRC_U4E (128+67) /* Vector: 49, UART4 Error */
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#define PIC32MX_IRQSRC_U4RX (128+68) /* Vector: 49, UART4 Receiver */
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#define PIC32MX_IRQSRC_U4TX (128+69) /* Vector: 49, UART4 Transmitter */
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#define PIC32MX_IRQSRC_U6E (128+70) /* Vector: 50, UART6 Error */
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#define PIC32MX_IRQSRC_U6RX (128+71) /* Vector: 50, UART6 Receiver */
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#define PIC32MX_IRQSRC_U6TX (128+72) /* Vector: 50, UART6 Transmitter */
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#define PIC32MX_IRQSRC_U5E (128+73) /* Vector: 51, UART5 Error */
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#define PIC32MX_IRQSRC_U5RX (128+74) /* Vector: 51, UART5 Receiver */
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#define PIC32MX_IRQSRC_U5TX (128+75) /* Vector: 51, UART5 Transmitter */
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#define PIC32MX_IRQSRC2_LAST (128+75)
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#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
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#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC2_LAST
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H */
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