109 lines
5.3 KiB
C
109 lines
5.3 KiB
C
/************************************************************************************
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* arch/hc/src/m9s12/m9s12_iic.h (v2)
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_M9S124_M9S124_IIC_H
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#define __ARCH_ARM_HC_SRC_M9S124_M9S124_IIC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_IIC_IBAD_OFFSET 0x0000 /* IIC Address Register */
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#define HCS12_IIC_IBFD_OFFSET 0x0001 /* IIC Frequency Divider Register */
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#define HCS12_IIC_IBCR_OFFSET 0x0002 /* IIC Control Register */
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#define HCS12_IIC_IBSR_OFFSET 0x0003 /* IIC Status Register */
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#define HCS12_IIC_IBDR_OFFSET 0x0004 /* IIC Data I/O Register */
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/* Register Addresses ***************************************************************/
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#define HCS12_IIC_IBAD (HCS12_IIC_BASE+HCS12_IIC_IBAD_OFFSET)
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#define HCS12_IIC_IBFD (HCS12_IIC_BASE+HCS12_IIC_IBFD_OFFSET)
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#define HCS12_IIC_IBCR (HCS12_IIC_BASE+HCS12_IIC_IBCR_OFFSET)
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#define HCS12_IIC_IBSR (HCS12_IIC_BASE+HCS12_IIC_IBSR_OFFSET)
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#define HCS12_IIC_IBDR (HCS12_IIC_BASE+HCS12_IIC_IBDR_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* IIC Address Register */
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#define IIC_IBAD_MASK (0xfe)
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/* IIC Frequency Divider Register -- 8-bit bus clock rate value */
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/* IIC Control Register */
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#define IIC_IBCR_IBSWAI (1 << 0) /* Bit 0: I Bus Interface Stop in Wait Mode */
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#define IIC_IBCR_RSTA (1 << 2) /* Bit 2: Repeat Start */
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#define IIC_IBCR_TXAK (1 << 3) /* Bit 3: Transmit Acknowledge Enable<6C> */
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#define IIC_IBCR_TX (1 << 4) /* Bit 4: Transmit/Receive Mode Select Bit */
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#define IIC_IBCR_MSSL (1 << 5) /* Bit 5: Master/Slave Mode Select Bit<69> */
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#define IIC_IBCR_IBIE (1 << 6) /* Bit 6: I-Bus Interrupt Enable */
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#define IIC_IBCR_IBEN (1 << 7) /* Bit 7: I-Bus Enable */
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/* IIC Status Register */
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#define IIC_IBSR_RXAK (1 << 0) /* Bit 0: Received Acknowledge */
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#define IIC_IBSR_IBIF (1 << 1) /* Bit 1: I-Bus Interrupt */
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#define IIC_IBSR_SRW (1 << 2) /* Bit 2: Slave Read/Write */
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#define IIC_IBSR_AL (1 << 4) /* Bit 4: Arbitration Lost */
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#define IIC_IBSR_BB (1 << 5) /* Bit 5: Bus Busy Bit */
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#define IIC_IBSR_AAS (1 << 6) /* Bit 6: Addressed as a Slave Bit */
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#define IIC_IBSR_TCF (1 << 7) /* Bit 7: Data Transferring Bit */
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/* IIC Data I/O Register -- 8-Bit data value */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_M9S124_M9S124_IIC_H */
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