141 lines
5.7 KiB
C
141 lines
5.7 KiB
C
/****************************************************************************
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* arch/arm/src/phy62xx/bus_dev.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Filename: bus_dev.h
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* Revised:
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* Revision:
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*
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* Description: This file contains the SoC MCU relate definitions
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_PHY62XX_BUS_DEV_H
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#define __ARCH_ARM_SRC_PHY62XX_BUS_DEV_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "mcu.h"
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#define PHY_MCU_TYPE MCU_BUMBEE_M0
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enum
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{
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RSTC_COLD_UP = 0,
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RSTC_WARM_UP = 1,
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RSTC_OFF_MODE = 2,
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RSTC_WAKE_IO = 3,
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RSTC_WAKE_RTC = 4,
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RSTC_WARM_NDWC = 5 /* user mode, no dwc */
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};
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/* ---- Interrupt Number Definition ---- */
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#if defined ( __CC_ARM )
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#define M0_IRQ_BASE 0
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#elif defined ( __GNUC__ )
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#define M0_IRQ_BASE 16
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#endif
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typedef enum IRQn
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{
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/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
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NonMaskableInt_IRQn = -14+M0_IRQ_BASE, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13+M0_IRQ_BASE, /* 3 HardFault Interrupt */
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SVCall_IRQn = -5+M0_IRQ_BASE, /* 11 SV Call Interrupt */
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PendSV_IRQn = -2+M0_IRQ_BASE, /* 14 Pend SV Interrupt */
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SysTick_IRQn = -1+M0_IRQ_BASE, /* 15 System Tick Interrupt */
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/* ---------------------- PHY BUMBEE M0 Interrupt Numbers --------------------- */
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BB_IRQn = 4+M0_IRQ_BASE, /* Base band Interrupt */
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KSCAN_IRQn = 5+M0_IRQ_BASE, /* Key scan Interrupt */
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RTC_IRQn = 6+M0_IRQ_BASE, /* RTC Timer Interrupt */
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WDT_IRQn = 10+M0_IRQ_BASE, /* Watchdog Timer Interrupt */
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UART0_IRQn = 11+M0_IRQ_BASE, /* UART0 Interrupt */
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I2C0_IRQn = 12+M0_IRQ_BASE, /* I2C0 Interrupt */
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I2C1_IRQn = 13+M0_IRQ_BASE, /* I2C1 Interrupt */
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SPI0_IRQn = 14+M0_IRQ_BASE, /* SPI0 Interrupt */
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SPI1_IRQn = 15+M0_IRQ_BASE, /* SPI1 Interrupt */
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GPIO_IRQn = 16+M0_IRQ_BASE, /* GPIO Interrupt */
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UART1_IRQn = 17+M0_IRQ_BASE, /* UART1 Interrupt */
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SPIF_IRQn = 18+M0_IRQ_BASE, /* SPIF Interrupt */
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DMAC_IRQn = 19+M0_IRQ_BASE, /* DMAC Interrupt */
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TIM1_IRQn = 20+M0_IRQ_BASE, /* Timer1 Interrupt */
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TIM2_IRQn = 21+M0_IRQ_BASE, /* Timer2 Interrupt */
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TIM3_IRQn = 22+M0_IRQ_BASE, /* Timer3 Interrupt */
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TIM4_IRQn = 23+M0_IRQ_BASE, /* Timer4 Interrupt */
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TIM5_IRQn = 24+M0_IRQ_BASE, /* Timer5 Interrupt */
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TIM6_IRQn = 25+M0_IRQ_BASE, /* Timer6 Interrupt */
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AES_IRQn = 28+M0_IRQ_BASE, /* AES Interrupt */
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ADCC_IRQn = 29+M0_IRQ_BASE, /* ADC Interrupt */
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QDEC_IRQn = 30+M0_IRQ_BASE, /* QDEC Interrupt */
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RNG_IRQn = 31+M0_IRQ_BASE /* RNG Interrupt */
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} IRQn_Type;
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#ifdef __cplusplus
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#define __I volatile /* < Defines 'read only' permissions */
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#else
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#define __I volatile const /* < Defines 'read only' permissions */
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#endif
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#define __O volatile /* < Defines 'write only' permissions */
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#define __IO volatile /* < Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /* Defines 'read only' structure member permissions */
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#define __OM volatile /* Defines 'write only' structure member permissions */
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#define __IOM volatile /* Defines 'read / write' structure member permissions */
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#define NVIC_DisableIRQ(irqid) up_disable_irq(irqid)
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#define NVIC_EnableIRQ(irqid) up_enable_irq(irqid)
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#define NVIC_SetPriority(i,p)
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#if 0
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#if (PHY_MCU_TYPE == MCU_BUMBEE_M0)
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#define ATTRIBUTE_ISR
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#include "core_bumbee_m0.h"
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#endif
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#if(PHY_MCU_TYPE == MCU_BUMBEE_CK802)
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#define ATTRIBUTE_ISR __attribute__((isr))
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#include "core_802.h"
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#endif
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#endif //0
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#if (PHY_MCU_TYPE == MCU_BUMBEE_M0 || PHY_MCU_TYPE == MCU_BUMBEE_CK802)
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#include "mcu_phy_bumbee.h"
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#elif ((PHY_MCU_TYPE == MCU_PRIME_A1) ||(PHY_MCU_TYPE == MCU_PRIME_A2))
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#include "mcu_phy_prime.h"
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#endif
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#endif /* __ARCH_ARM_SRC_PHY62XX_BUS_DEV_H */
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