7c5b2e3305
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
77 lines
2.4 KiB
C
77 lines
2.4 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-m/arm_perf.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/arch.h>
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#include <nuttx/clock.h>
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#include "arm_internal.h"
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#include "dwt.h"
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#include "itm.h"
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#include "nvic.h"
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static uint32_t g_cpu_freq;
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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void up_perf_init(void *arg)
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{
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g_cpu_freq = (uint32_t)(uintptr_t)arg;
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/* Enable ITM and DWT resources, if not left enabled by debugger. */
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modifyreg32(NVIC_DEMCR, 0, NVIC_DEMCR_TRCENA);
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/* Make sure the high speed cycle counter is running. It will be started
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* automatically only if a debugger is connected.
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*/
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putreg32(0xc5acce55, ITM_LAR);
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modifyreg32(DWT_CTRL, 0, DWT_CTRL_CYCCNTENA_MASK);
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}
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uint32_t up_perf_getfreq(void)
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{
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return g_cpu_freq;
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}
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uint32_t up_perf_gettime(void)
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{
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return getreg32(DWT_CYCCNT);
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}
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void up_perf_convert(uint32_t elapsed, struct timespec *ts)
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{
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uint32_t left;
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ts->tv_sec = elapsed / g_cpu_freq;
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left = elapsed - ts->tv_sec * g_cpu_freq;
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ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq;
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}
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