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f7af996f1d
nuttx/arch/arm/include
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Alin Jerpelea f7af996f1d Merged in alinjerpelea/nuttx (pull request #1059) 
boards: cxd56xx: spresense: add board_timerhook function

* boards: cxd56xx: spresense: add board_timerhook function

    in preparation for SDK we muts have a weak board_timerhook function

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* drivers: usbhost: add missing endif

    By accident an endif was missing.

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* boards: cxd56xx: audio: add build barrier

    The audio implementation should not be beuilt if the config
    CONFIG_CXD56_AUDIO is not set.

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* arch:arm:cxd56xx: add ge2d.h header

    The header is used by imageproc.

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-10-23 13:12:21 +00:00
..
a1x Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
am335x arch/arm/include/amm335x: Trivial, cosmetic changes after review 2019-01-08 08:15:04 -06:00
arm Squashed commit of the following: 2019-04-29 14:52:05 -06:00
armv6-m Squashed commit of the following: 2019-04-29 14:52:05 -06:00
armv7-a Squashed commit of the following: 2019-04-29 14:52:05 -06:00
armv7-m This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts? 2019-08-09 10:52:35 -06:00
armv7-r Squashed commit of the following: 2019-04-29 14:52:05 -06:00
c5471 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
cxd56xx Merged in alinjerpelea/nuttx (pull request #1059) 2019-10-23 13:12:21 +00:00
dm320 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
efm32 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
imx1 i.MX6: Add IRQ header file 2016-02-28 14:07:53 -06:00
imx6 Fix lots of typos in C comments and Kconfig help text 2018-07-08 18:24:45 -06:00
imxrt Merged imxrt1020 into master 2019-04-30 16:08:46 -06:00
kinetis Merged in dagar/nuttx/pr-kinetic_minor_fix (pull request #820) 2019-01-19 15:39:46 +00:00
kl arch/: Clean up some naming and spacing. 2018-06-20 15:38:06 -06:00
lc823450 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
lpc17xx_40xx Merged in jjlange/nuttx/lpc40xx (pull request #946) 2019-07-11 16:50:00 +00:00
lpc31xx Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
lpc43xx In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
lpc54xx symtab/Makefile: When system wide locale is set (i.e. en_US.UTF-8) then 'read' is ordered after 'readdir' even if separator is set to quotation mark and key set to 2. When C locale is used result is correct. 2019-08-14 11:02:30 -06:00
lpc214x Fix names of pre-processor variables used in header file idempotence 2016-08-06 18:48:45 -06:00
lpc2378 Fix names of pre-processor variables used in header file idempotence 2016-08-06 18:48:45 -06:00
max326xx In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
moxart Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
nrf52 arch/arm/include/nrf52/ and arch/arm/src/nrf52: 1. Added 52840 family support 2. Use common irq and memory layout header file for 52832 & 52840. 2019-03-12 09:43:49 -06:00
nuc1xx Cosmetic changes to spacing and comments. 2017-04-20 14:08:08 -06:00
s32k1xx arch/arm/src/s32k1xx: This commit brings in the LPSPI and LPI2C peripheral drivers from the i.MXRT which used the identical IP. 2019-08-21 11:18:40 -06:00
sam34 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
sama5 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
samd2l2 Rename all usage of samdl/SAMDL to samd2l2/SAMD2L2 to make room in the name space for the forthcoming samd5e5/SAMD5E5 2018-07-22 15:54:12 -06:00
samd5e5 configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional. 2018-09-01 15:29:22 -06:00
samv7 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
stm32 Merged in raiden00/nuttx_pe (pull request #796) 2019-01-02 12:12:28 +00:00
stm32f0l0g0 Add support for STM32G070xx 2019-09-17 11:10:38 -06:00
stm32f7 *Merged in zhoukejun/nuttx_nucleo-f767zi (pull request #838) 2019-03-11 03:44:57 +00:00
stm32h7 arch/arm/src/stm32h7/: Add stm32h7 ethernet driver. This is the initial push for the ethernet driver. The driver has been tested to be working on a nucleo board. This is still WIP, it doesn't for example do MAC filtering on HW level, but just receives all ethernet packets. 2019-04-30 08:43:39 -06:00
stm32l4 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
str71x Clean up and review of header files for conformance to standards 2015-06-12 19:26:01 -06:00
tiva Tiva directories: Fix TM4C129XNCZAD part number in Kconfig and identifiers. Rationale: Fully specify that this is the 212-pin BGA package (ZAD ending) and for consistency with earlier changes to other Tiva TM4C12x part numbers in Kconfig names and identifiers. 2019-08-30 08:46:57 -06:00
tms570 arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues 2018-04-18 08:58:36 -06:00
xmc4 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
.gitignore Move LPC17xx IOCON register definitions from lpc17_gpio.h to lpc17_iocon.h; fix a few more .gitignore files 2013-04-04 18:12:44 -06:00
arch.h Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
elf.h arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR. 2019-01-26 07:43:31 -06:00
inttypes.h Add architecture-specific inttypes.h 2016-10-27 16:01:38 -04:00
irq.h arch/arm: Add the initial cortex-a7 archtiecture support 2019-03-19 11:51:29 -06:00
limits.h Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
setjmp.h arch/arm/src/armv7-m: Add ARMv7-M setjmp/longjump functions. 2019-08-06 15:59:19 -06:00
spinlock.h Fix some typos 2019-09-17 10:46:23 -06:00
stdarg.h Add a generic GCC stdarg.h header file 2012-07-08 14:50:43 +00:00
syscall.h arch/arm: Add the initial cortex-a7 archtiecture support 2019-03-19 11:51:29 -06:00
tls.h TLS: Forgot to add a file before last commit 2016-03-11 12:30:04 -06:00
types.h Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00