Jukka Laitinen f9b5918462 arch/risc-v/src/mpfs/mpfs_ddr.c: Make sure that DDRC is in reset when starting the training ...

Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

2023-08-30 12:28:21 +03:00

..

include

arch/risc-v: Add support for StarFive JH7110 SoC

2023-08-03 22:55:55 -07:00

src

arch/risc-v/src/mpfs/mpfs_ddr.c: Make sure that DDRC is in reset when starting the training

2023-08-30 12:28:21 +03:00

Kconfig

risc-v/litex: Add system reset and access to core control registers.

2023-08-25 17:16:28 +08:00