Inochi Amaoto 0ddcbe62ec arch/risc-v: does not clear IPI address in S mode ... According to the riscv-aclint doc, writing 0 to SSWI address has no effect. Remove this unnecessary write for S mode. Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Inochi Amaoto <inochiama@outlook.com>		2024-07-18 22:59:29 +08:00
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include	riscv: Initial support for debug trigger module	2024-07-14 20:32:19 +08:00
src	arch/risc-v: does not clear IPI address in S mode	2024-07-18 22:59:29 +08:00
CMakeLists.txt	cmake:init RISC-V cmake qemu-rv build	2023-10-26 21:01:46 +08:00
Kconfig	riscv: Initial support for debug trigger module	2024-07-14 20:32:19 +08:00