347 lines
11 KiB
C
347 lines
11 KiB
C
/****************************************************************************
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* boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* References:
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* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
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* - NXP lpc313x.cdl.drivers.zip example driver code
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "arm_internal.h"
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#include "lpc31_syscreg.h"
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#include "lpc31_cgudrvr.h"
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#include "lpc31_mpmc.h"
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#include "ea3131.h"
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#ifdef CONFIG_LPC31_EXTDRAM
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The MPMC delay based on trace lengths between SDRAM and the chip and on
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* the delay strategy used for SDRAM.
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*/
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#define EA3131_MPMC_DELAY 0x824
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/* Delay constants in nanosecondss for MT48LC32M16LF SDRAM on board */
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#define EA3131_SDRAM_TRP (20)
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#define EA3131_SDRAM_TRFC (66)
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#define EA3131_SDRAM_TRAS (44)
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#define EA3131_SDRAM_TREX (75)
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#define EA3131_SDRAM_TARP 4
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#define EA3131_SDRAM_TWR (75)
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#define EA3131_SDRAM_TRC (66)
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#define EA3131_SDRAM_TRRD (15)
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#define EA3131_SDRAM_TMRD (20)
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#define EA3131_SDRAM_TXSR (75)
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#define EA3131_SDRAM_TDAL (50)
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#define EA3131_SDRAM_REFRESH (100)
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#define EA3131_SDRAM_OPERREFRESH (7812)
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/* Macro used to convert the above values (in nanoseconds) into units of
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* the HCLK.
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*/
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#define NS2HCLKS(ns, hclk2, mask) \
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((uint32_t)(((uint64_t)ns *(uint64_t)hclk2) / 1000000000ull) & mask)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc31_sdraminitialize
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*
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* Description:
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* Configure SDRAM on the EA3131 board
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*
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* Micron Initialization Sequence from their data sheet for the Micron
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* MT48LC32M16A2 32M x 16 SDRAM chip:
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*
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* "SDRAMs must be powered up and initialized in a predefined manner.
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* Operational procedures other than those specified may result in
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* undefined operation. Once power is applied to VDD and VDDQ
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* (simultaneously) and the clock is stable (stable clock is defined as
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* a signal cycling within timing constraints specified for the clock
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* pin), the SDRAM requires a 100µs delay prior to issuing any command
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* other than a COMMAND INHIBIT or NOP.
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*
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* "Starting at some point during this 100µs period and continuing at
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* least through the end of this period, COMMAND INHIBIT or NOP commands
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* should be applied. Once the 100µs delay has been satisfied with at
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* least one COMMAND INHIBIT or NOP command having been applied, a
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* PRECHARGE command should be applied. All banks must then be precharged,
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* thereby placing the device in the all banks idle state.
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*
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* "Once in the idle state, two AUTO REFRESH cycles must be performed.
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* After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
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* register programming.
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*
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* "Because the mode register will power up in an unknown state, it should
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* be loaded prior to applying any operational command."
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*
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* The JEDEC recommendation for initializing SDRAM is:
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*
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* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
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* Wait 200uS
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* PRECHARGE all
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* 8 AUTO REFRESH COMMANDS
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* LOAD MODE REGISTER
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* SDRAM is ready for operation
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*
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* The Micron SDRAM parts will work fine with the JEDEC sequence, but also
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* allow for a quicker init sequence of:
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*
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* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
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* Wait at least 100uS (during which time start applying and
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* continue applying NOP or COMMAND INHIBIT)
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* PRECHARGE all
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* 2 AUTO REFRESH COMMANDS (min requirement, more than 2 is also ok)
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* LOAD MODE REGISTER
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* SDRAM is ready for operation
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*
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****************************************************************************/
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static void lpc31_sdraminitialize(void)
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{
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uint32_t regval;
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/* These run-time calculations can be reduced dramatically if hclk is
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* replaced with an apriori value.
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*/
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#ifdef CONFIG_LPC31_SDRAMHCLK
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# define HCLK CONFIG_LPC31_SDRAMHCLK
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#else
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uint32_t hclk = lpc31_clkfreq(CLKID_MPMCCFGCLK2, DOMAINID_SYS);
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# define HCLK hclk
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#endif
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/* Check RTL for divide by 2 possible.
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* If so change then enable the following logic
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*/
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#if 0
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uint32_t hclk2 = hclk;
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if (((getreg32(LPC31_MPMC_CONFIG) & MPMC_CONFIG_CLK)) != 0)
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{
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hclk2 >>= 1;
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}
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# define HCLK2 hclk2
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#else
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# define HCLK2 hclk
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#endif
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up_udelay(100);
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/* Set command delay startergy */
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putreg32(MPMC_DYNREADCONFIG_CMDDEL, LPC31_MPMC_DYNREADCONFIG);
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/* Configure device config register nSDCE0 for proper width SDRAM */
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putreg32((MPMC_DYNCONFIG0_MDSDRAM | MPMC_DYNCONFIG_HP16_32MX16),
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LPC31_MPMC_DYNCONFIG0);
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putreg32((MPMC_DYNRASCAS0_RAS2CLK | MPMC_DYNRASCAS0_CAS2CLK),
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LPC31_MPMC_DYNRASCAS0);
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/* Min 20ns program 1 so that at least 2 HCLKs are used */
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putreg32(NS2HCLKS(EA3131_SDRAM_TRP, HCLK2, MPMC_DYNTRP_MASK),
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LPC31_MPMC_DYNTRP);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRAS, HCLK2, MPMC_DYNTRAS_MASK),
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LPC31_MPMC_DYNTRAS);
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putreg32(NS2HCLKS(EA3131_SDRAM_TREX, HCLK2, MPMC_DYNTSREX_MASK),
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LPC31_MPMC_DYNTSREX);
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putreg32(EA3131_SDRAM_TARP,
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LPC31_MPMC_DYNTAPR);
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putreg32(NS2HCLKS(EA3131_SDRAM_TDAL, HCLK2, MPMC_DYNTDAL_MASK),
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LPC31_MPMC_DYNTDAL);
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putreg32(NS2HCLKS(EA3131_SDRAM_TWR, HCLK2, MPMC_DYNTWR_MASK),
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LPC31_MPMC_DYNTWR);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRC, HCLK2, MPMC_DYNTRC_MASK),
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LPC31_MPMC_DYNTRC);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRFC, HCLK2, MPMC_DYNTRFC_MASK),
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LPC31_MPMC_DYNTRFC);
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putreg32(NS2HCLKS(EA3131_SDRAM_TXSR, HCLK2, MPMC_DYNTXSR_MASK),
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LPC31_MPMC_DYNTXSR);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRRD, HCLK2, MPMC_DYNTRRD_MASK),
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LPC31_MPMC_DYNTRRD);
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putreg32(NS2HCLKS(EA3131_SDRAM_TMRD, HCLK2, MPMC_DYNTMRD_MASK),
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LPC31_MPMC_DYNTMRD);
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up_udelay(100);
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/* Issue continuous NOP commands */
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putreg32((MPMC_DYNCONTROL_CE | MPMC_DYNCONTROL_CS |
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MPMC_DYNCONTROL_INOP), LPC31_MPMC_DYNCONTROL);
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/* Wait ~200us */
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up_udelay(200);
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/* Issue a "pre-charge all" command */
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putreg32((MPMC_DYNCONTROL_CE | MPMC_DYNCONTROL_CS |
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MPMC_DYNCONTROL_IPALL), LPC31_MPMC_DYNCONTROL);
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/* Minimum refresh pulse interval (tRFC) for MT48LC32M16A2=80nsec,
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* 100nsec provides more than adequate interval.
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*/
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putreg32(NS2HCLKS(EA3131_SDRAM_REFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK),
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LPC31_MPMC_DYNREFRESH);
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/* Wait ~250us */
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up_udelay(250);
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/* Recommended refresh interval for normal operation of the Micron
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* MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) =
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* refresh counter interval rate, (subtract one for safety margin).
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*/
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putreg32(NS2HCLKS(EA3131_SDRAM_OPERREFRESH, HCLK,
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MPMC_DYNREFRESH_TIMER_MASK), LPC31_MPMC_DYNREFRESH);
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/* Select mode register update mode */
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putreg32((MPMC_DYNCONTROL_CE | MPMC_DYNCONTROL_CS |
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MPMC_DYNCONTROL_IMODE), LPC31_MPMC_DYNCONTROL);
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/* Program the SDRAM internal mode registers on bank nSDCE0 and reconfigure
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* the SDRAM chips.
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* Bus speeds up to 90MHz requires use of a CAS latency = 2.
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* To get correct value on address bus CAS cycle, requires a shift by 13
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* for 16bit mode
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*/
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getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
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putreg32((MPMC_DYNCONFIG0_MDSDRAM | MPMC_DYNCONFIG_HP16_32MX16),
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LPC31_MPMC_DYNCONFIG0);
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putreg32((MPMC_DYNRASCAS0_RAS2CLK | MPMC_DYNRASCAS0_CAS2CLK),
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LPC31_MPMC_DYNRASCAS0);
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/* Select normal operating mode */
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putreg32((MPMC_DYNCONTROL_CE | MPMC_DYNCONTROL_CS |
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MPMC_DYNCONTROL_INORMAL), LPC31_MPMC_DYNCONTROL);
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/* Enable buffers */
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regval = getreg32(LPC31_MPMC_DYNCONFIG0);
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regval |= MPMC_DYNCONFIG0_B;
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putreg32(regval, LPC31_MPMC_DYNCONFIG0);
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putreg32((MPMC_DYNCONTROL_INORMAL | MPMC_DYNCONTROL_CS),
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LPC31_MPMC_DYNCONTROL);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc31_meminitialize
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*
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* Description:
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* Initialize external memory resources (sram, sdram, nand, nor, etc.)
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*
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****************************************************************************/
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void lpc31_meminitialize(void)
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{
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/* Configure the LCD pins in external bus interface (EBI/MPMC) memory mode.
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*
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* LCD_CSB -> MPMC_NSTCS_0
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* LCD_DB_1 -> MPMC_NSTCS_1
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* LCD_DB_0 -> MPMC_CLKOUT
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* LCD_E_RD -> MPMC_CKE
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* LCD_RS -> MPMC_NDYCS
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* LCD_RW_WR -> MPMC_DQM_1
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* LCD_DB_2 -> EBI_A_2
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* LCD_DB_3 -> EBI_A_3 l
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* LCD_DB_4 -> EBI_A_4 l
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* LCD_DB_5 -> EBI_A_5 l
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* LCD_DB_6 -> EBI_A_6
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* LCD_DB_7 -> EBI_A_7
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* LCD_DB_8 -> EBI_A_8
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* LCD_DB_9 -> EBI_A_9
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* LCD_DB_10 -> EBI_A_10
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* LCD_DB_11 -> EBI_A_11
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* LCD_DB_12 -> EBI_A_12
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* LCD_DB_13 -> EBI_A_13
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* LCD_DB_14 -> EBI_A_14
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* LCD_DB_15 -> EBI_A_15
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*/
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putreg32(SYSCREG_MUX_LCDEBISEL_EBIMPMC, LPC31_SYSCREG_MUX_LCDEBISEL);
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/* Enable EBI clock */
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lpc31_enableclock(CLKID_EBICLK);
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/* Enable MPMC controller clocks */
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lpc31_enableclock(CLKID_MPMCCFGCLK);
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lpc31_enableclock(CLKID_MPMCCFGCLK2);
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lpc31_enableclock(CLKID_MPMCCFGCLK3);
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/* Enable the external memory controller */
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putreg32(MPMC_CONTROL_E, LPC31_MPMC_CONTROL);
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/* Force HCLK to MPMC_CLK to 1:1 ratio, little-endian mode */
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putreg32(0, LPC31_MPMC_CONFIG);
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/* Set MPMC delay based on trace lengths between SDRAM and the chip
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* and on the delay strategy used for SDRAM.
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*/
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putreg32(EA3131_MPMC_DELAY, LPC31_SYSCREG_MPMC_DELAYMODES);
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/* Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board */
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lpc31_sdraminitialize();
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}
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#endif /* CONFIG_LPC31_EXTDRAM */
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