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Jukka Laitinen fc41bb7f8a boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET 
This fixes problems with DDR training sequence on aries m100pfs board

    - Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2)
    - Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-29 09:36:49 -06:00
..
bl602/bl602evb arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00
c906/smartl-c906 arch/risc-v: Remove unneeded kconfigs 2021-12-28 05:02:42 -06:00
esp32c3/esp32c3-devkit arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00
fe310/hifive1-revb arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00
k210/maix-bit arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00
litex/arty_a7 arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00
mpfs boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET 2021-12-29 09:36:49 -06:00
qemu-rv32/rv32-virt arch/risc-v: Remove unneeded kconfigs 2021-12-28 05:02:42 -06:00
rv32m1/rv32m1-vega arch/risc-v: Remove unneeded kconfigs 2021-12-28 05:02:42 -06:00