fae7e63479
1. Serial (UART) driver (13 ports) 2. Ethernet driver This port is provided on two boards 1. RSK RX65N-2MB 2. GR-Rose The port is built on Cygwin environment. As part of this port, we have created two documents 1. Readme.txt for each board 2. User manual to provide information about development environment setup Both these documents are placed under 1. /boards/renesas/rx65n/rx65n-grrose 2. /boards/renesas/rx65n/rx65n-rsk2mb We have run 'nxstyle' for coding guidelines and 'ostest' for testing NuttX features on test platform. We have shared the log with no errors as confirmation of valid port.
169 lines
2.5 KiB
Plaintext
169 lines
2.5 KiB
Plaintext
MEMORY
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{
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/* RSK-RX65N-1MB */
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/*
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RAM : ORIGIN = 0x0, LENGTH = 262144
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ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576
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OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
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*/
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/* RSK-RX65N-2MB | GR-ROSE */
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RAM : ORIGIN = 0x0, LENGTH = 262144
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RAMHI : ORIGIN = 0x800000, LENGTH = 393216
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ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
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OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256
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}
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SECTIONS
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{
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.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
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{
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KEEP(*(.exvectors))
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} > ROM
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.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
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{
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KEEP(*(.fvectors))
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} > ROM
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/* RSK-RX65N-1MB */
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/*
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.text 0xFFF00000: AT(0xFFF00000)
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*/
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/* RSK-RX65N-2MB | GR-ROSE */
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.text 0xFFE00000: AT(0xFFE00000)
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{
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*(.text)
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. = ALIGN(4);
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*(.text.*)
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. = ALIGN(4);
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*(P)
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etext = .;
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} > ROM
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.rvectors :
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{
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_rvectors_start = .;
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KEEP(*(.rvectors))
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_rvectors_end = .;
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} > ROM
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.init :
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{
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KEEP(*(.init))
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__preinit_array_start = .;
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KEEP(*(.preinit_array))
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__preinit_array_end = .;
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__init_array_start = (. + 3) & ~ 3;
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KEEP(*(.init_array))
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KEEP(*(SORT(.init_array.*)))
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__init_array_end = .;
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__fini_array_start = .;
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KEEP(*(.fini_array))
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KEEP(*(SORT(.fini_array.*)))
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__fini_array_end = .;
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} > ROM
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.fini :
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{
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KEEP(*(.fini))
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} > ROM
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.got :
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{
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*(.got)
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*(.got.plt)
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} > ROM
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.rodata :
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{
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*(.rodata)
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*(.rodata.*)
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*(C_1)
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*(C_2)
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*(C)
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_erodata = .;
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} > ROM
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.eh_frame_hdr :
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{
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*(.eh_frame_hdr)
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} > ROM
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.eh_frame :
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{
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*(.eh_frame)
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} > ROM
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.jcr :
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{
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*(.jcr)
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} > ROM
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.tors :
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{
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__CTOR_LIST__ = .;
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. = ALIGN(2);
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___ctors = .;
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*(.ctors)
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___ctors_end = .;
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__CTOR_END__ = .;
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__DTOR_LIST__ = .;
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___dtors = .;
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*(.dtors)
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___dtors_end = .;
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__DTOR_END__ = .;
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. = ALIGN(2);
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_mdata = .;
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} > ROM
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.ustack 0x400: AT(0x200)
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{
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_ustack = .;
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} > RAM
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.istack 0x200: AT(0x200)
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{
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_istack = .;
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} > RAM
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.data 0x404: AT(_mdata)
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{
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_data = .;
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*(.data)
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*(.data.*)
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*(D)
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*(D_1)
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*(D_2)
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_edata = .;
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} > RAM
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.gcc_exc :
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{
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*(.gcc_exc)
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} > RAM
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.bss :
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{
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_bss = .;
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*(.bss)
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*(.bss.**)
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*(COMMON)
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*(B)
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*(B_1)
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*(B_2)
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_ebss = .;
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_end = .;
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} > RAM
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.ofs1 0xFE7F5D40: AT(0xFE7F5D00)
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{
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KEEP(*(.ofs1))
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} > OFS
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.ofs2 0xFE7F5D48: AT(0xFE7F5D10)
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{
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KEEP(*(.ofs2))
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} > OFS
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.ofs3 0xFE7F5D50: AT(0xFE7F5D40)
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{
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KEEP(*(.ofs3))
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} > OFS
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.ofs4 0xFE7F5D10: AT(0xFE7F5D48)
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{
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KEEP(*(.ofs4))
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} > OFS
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.ofs5 0xFE7F5D10: AT(0xFE7F5D50)
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{
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KEEP(*(.ofs5))
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} > OFS
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.ofs6 0xFE7F5D10: AT(0xFE7F5D64)
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{
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KEEP(*(.ofs6))
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} > OFS
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.ofs7 0xFE7F5D10: AT(0xFE7F5D70)
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{
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KEEP(*(.ofs7))
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} > OFS
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}
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