e5dfd805e6
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
167 lines
4.7 KiB
INI
167 lines
4.7 KiB
INI
### From /usr/local/share/openocd/scripts/interface/olimex-arm-usb-ocd.cfg
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#
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# Olimex ARM-USB-OCD
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#
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# http://www.olimex.com/dev/arm-usb-ocd.html
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#
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interface ft2232
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ft2232_device_desc "Olimex OpenOCD JTAG A"
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ft2232_layout olimex-jtag
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ft2232_vid_pid 0x15ba 0x0003
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### From /usr/local/share/openocd/scripts/targets/lpc40xx.cfg
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# NXP LPC4088 Cortex-M4 with 512kB Flash and 96kB Local On-Chip SRAM
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# remember to place in the same folder as lpc17xx.cfg
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set CHIPNAME lpc4088
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set CPUTAPID 0x410fc241
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set CPURAMSIZE 0x18000
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set CPUROMSIZE 0x80000
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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set CCLK 12000
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### From /usr/local/share/openocd/scripts/targets/lpc17xx.cfg
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### With additions to set the operating frequency to 120MHz
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# Common LPC17xx logic
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# LPC17xx chips support both JTAG and SWD transports.
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# JTAG is hard-coded in this configuration
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# Adapt based on what transport is active.
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# source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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error "_CHIPNAME not set"
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}
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK] } {
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set _CCLK $CCLK
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} else {
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set _CCLK 4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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error "_CPUTAPID not set"
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}
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if { [info exists CPURAMSIZE] } {
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set _CPURAMSIZE $CPURAMSIZE
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} else {
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error "_CPURAMSIZE not set"
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}
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if { [info exists CPUROMSIZE] } {
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set _CPUROMSIZE $CPUROMSIZE
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} else {
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error "_CPUROMSIZE not set"
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}
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#delays on reset lines
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adapter_nsrst_delay 500
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jtag_ntrst_delay 500
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# Use of JTAG is hard-coded
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#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
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# The LPC17xx devices have 32/64/128/256/512kB of flash memory, managed by ROM code
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# (including a boot loader which verifies the flash exception table's checksum).
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# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
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lpc1700 $_CCLK calc_checksum
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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adapter_khz 1000
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$_TARGETNAME configure -event reset-init {
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echo "Going to 120MHz"
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# PLL0CON: Disable PLL
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mww 0x400FC080 0x00000000
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# PLLFEED
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mww 0x400FC08C 0x000000AA
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# PLLFEED
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mww 0x400FC08C 0x00000055
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# CLKSEL: internal 12MHz RC oscillator Div 1.
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mww 0x400FC104 0x00000001
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# CLKSRCSEL: Clock source = internal 12MHz RC oscillator
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mww 0x400FC10C 0x00000000
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# PLL0CFG: M=10,P=1 -> PLL=240 MHz
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mww 0x400FC084 0x00000009
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# PLLFEED
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mww 0x400FC08C 0x000000AA
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# PLLFEED
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mww 0x400FC08C 0x00000055
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# PLL0CON: Enable PLL
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mww 0x400FC080 0x00000001
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# PLLFEED
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mww 0x400FC08C 0x000000AA
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# PLLFEED
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mww 0x400FC08C 0x00000055
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sleep 50
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# PLL0CON: Connect PLL
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# CCLKSEL=PLLED(240MHz)/2 (=120 MHz)
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mww 0x400FC104 0x00000102
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# PLLFEED
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mww 0x400FC08C 0x000000AA
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# PLLFEED
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mww 0x400FC08C 0x00000055
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# Dividing CPU clock by 8 should be pretty conservative
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#
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#
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adapter_khz 1500
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
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# Bit Symbol Value Description Reset
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# value
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# 0 MAP Memory map control. 0
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# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
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# 1 User mode. The on-chip Flash memory is mapped to address 0.
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# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
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#
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# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
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mww 0x400FC040 0x01
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}
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# if srst is not fitted use VECTRESET to
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# perform a soft reset - SYSRESETREQ is not supported
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cortex_m3 reset_config vectreset
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