fe44ce0f3f
This fixes the following 3 issues: 1. Wait for send to complete in exchange Before shutting down the SPI, we have to wait for send to complete; not only DMA, since DMA just puts data to the SPI fifo. It is not yet out of SPI. When doing exchange with both send & receive this is not an issue because when receive dma has completed, it is certain that also the send is. This can be accomplished by completing the transfer in SPI TXC interrupt instead of DMA callback. 2. Fix TXDMAEN and RXDMAEN placement According to the spec, the RXDMAEN must be enabled before enabling DMA requests for Tx and Rx in DMA registers, and TXDMAEN after that. Cleaner place to do this is in spi_dmarxstart and spi_dmatxstart, where also the dma requests are enabled. This also handles properly the simplex modes. 3. Remove bus signal glitches when shutting off SPI block Use AFCNTR to avoid glitches in SPI lines while turning SPI block on/off during calls to exchange. Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com> |
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