495 lines
15 KiB
C
495 lines
15 KiB
C
/****************************************************************************
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* drivers/mtd/mtd_nandram.c
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* This file deals with the raw lower half of the device driver, and manages
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* reading and writing to the actual NAND Flash device that has been emulated
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* from RAM.
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <debug.h>
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#include <stddef.h>
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#include <nuttx/compiler.h>
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#include <nuttx/mutex.h>
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#include <nuttx/mtd/nand_ram.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_MTD_NAND_RAM_DEBUG
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#define NAND_RAM_DEBUG_1 1
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#define NAND_RAM_DEBUG_2 5
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#define NAND_RAM_DEBUG_3 10
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#define NAND_RAM_STATUS_1 1
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#define NAND_RAM_STATUS_2 5
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#define NAND_RAM_STATUS_3 10
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#define NAND_RAM_STATUS_4 50
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#define NAND_RAM_STATUS_5 100
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#define NAND_RAM_STATUS_6 500
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#define NAND_RAM_STATUS_7 1000
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#define NAND_RAM_STATUS_8 5000
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#define NAND_RAM_STATUS_9 10000
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#define NAND_RAM_STATUS_10 50000
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#if CONFIG_MTD_NAND_RAM_DEBUG_LEVEL == 1
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#define NAND_RAM_DEBUG_LEVEL NAND_RAM_DEBUG_1
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#elif CONFIG_MTD_NAND_RAM_DEBUG_LEVEL == 2
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#define NAND_RAM_DEBUG_LEVEL NAND_RAM_DEBUG_2
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#elif CONFIG_MTD_NAND_RAM_DEBUG_LEVEL == 3
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#define NAND_RAM_DEBUG_LEVEL NAND_RAM_DEBUG_3
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#endif /* CONFIG_MTD_NAND_RAM_DEBUG_LEVEL */
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#if CONFIG_MTD_NAND_RAM_STATUS == 1
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_1
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#elif CONFIG_MTD_NAND_RAM_STATUS == 2
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_2
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#elif CONFIG_MTD_NAND_RAM_STATUS == 3
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_3
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#elif CONFIG_MTD_NAND_RAM_STATUS == 4
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_4
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#elif CONFIG_MTD_NAND_RAM_STATUS == 5
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_5
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#elif CONFIG_MTD_NAND_RAM_STATUS == 6
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_6
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#elif CONFIG_MTD_NAND_RAM_STATUS == 7
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_7
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#elif CONFIG_MTD_NAND_RAM_STATUS == 8
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_8
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#elif CONFIG_MTD_NAND_RAM_STATUS == 9
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_9
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#elif CONFIG_MTD_NAND_RAM_STATUS == 10
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#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_10
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#endif /* CONFIG_MTD_NAND_RAM_STATUS */
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#define NAND_RAM_LOG(str, ...) \
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{ \
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if (nand_ram_ins_i % NAND_RAM_DEBUG_LEVEL == 0) \
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{ \
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syslog(LOG_DEBUG, "nand_ram: " str, __VA_ARGS__); \
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} \
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} \
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#define NAND_RAM_STATUS_LOG(str, ...) \
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syslog(LOG_DEBUG, "nand_ram_status: " str, __VA_ARGS__);
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#else
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#define NAND_RAM_LOG(str, ...)
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#define NAND_RAM_STATUS_LOG(str, ...)
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#endif /* CONFIG_MTD_NAND_RAM_DEBUG */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct nand_ram_data_s
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{
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uint8_t page[NAND_RAM_PAGE_SIZE];
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};
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/* 512 B page spare scheme */
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struct nand_ram_spare_s
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{
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uint8_t ecc_0; /* 0 */
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uint8_t ecc_1;
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uint8_t ecc_2;
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uint8_t ecc_3;
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uint8_t __res1;
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uint8_t bad; /* 5 */ /* NAND_RAM_BLOCK_* */
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uint8_t ecc_4;
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uint8_t ecc_5;
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/* Using reserved (8 bytes) */
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uint16_t n_read;
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uint16_t n_write; /* 10 */
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uint16_t n_erase;
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uint8_t free; /* Erased page: NAND_RAM_PAGE_* */
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uint8_t __res2;
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static uint64_t nand_ram_ins_i = 0; /* Instruction counter */
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static mutex_t nand_ram_dev_mut;
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static struct nand_ram_data_s nand_ram_flash_data[NAND_RAM_N_PAGES];
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static struct nand_ram_spare_s nand_ram_flash_spare[NAND_RAM_N_PAGES];
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/* Hard coded array for bad block indexes */
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static int g_nand_ram_rand_bad_blk_indx[] =
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{
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4, 14, 19, 21, 28, 30, 107,
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108, 164, 173, 179, 229, 268,
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362, 377, 382, 396, 410, 412,
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419, 428, 456, 500, 0
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* External Functions
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nand_ram_storage_status
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*
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* Description:
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* Writes per-page status of virtual NAND Flash.
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*
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****************************************************************************/
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static void nand_ram_storage_status(void)
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{
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uint32_t i;
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uint16_t reads;
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uint16_t writes;
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uint16_t erases;
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uint8_t bad;
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/* Wear */
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for (i = 0; i < NAND_RAM_N_PAGES; i++)
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{
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reads = nand_ram_flash_spare[i].n_read;
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writes = nand_ram_flash_spare[i].n_write;
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erases = nand_ram_flash_spare[i].n_erase;
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bad = (nand_ram_flash_spare[i].bad != NAND_RAM_BLOCK_GOOD);
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NAND_RAM_STATUS_LOG(
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"Block %3" PRIi32 ", Page %6" PRIi32 ", Bad: %1" PRIi32 " |"
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" Reads: %6" PRIi32 ", Writes: %6" PRIi32 ", Erases: %6" PRIi32 "\n",
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i >> NAND_RAM_LOG_PAGES_PER_BLOCK, i, bad,
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reads, writes, erases);
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}
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return;
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}
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static inline void nand_ram_status(void)
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{
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#ifdef CONFIG_MTD_NAND_RAM_DEBUG
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if (nand_ram_ins_i % NAND_RAM_STATUS_LEVEL == 0)
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{
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nand_ram_storage_status();
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}
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#endif
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}
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/****************************************************************************
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* Name: nand_ram_storage_init
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*
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* Description:
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* Initializes the actual NAND Device that is emulated from RAM.
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*
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****************************************************************************/
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static void nand_ram_storage_init(void)
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{
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int i;
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memset(nand_ram_flash_data, 0xff,
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sizeof(struct nand_ram_data_s) * NAND_RAM_N_PAGES);
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memset(nand_ram_flash_spare, 0,
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sizeof(struct nand_ram_spare_s) * NAND_RAM_N_PAGES);
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for (i = 0; i < NAND_RAM_N_PAGES; i++)
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{
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nand_ram_flash_spare[i].free = NAND_RAM_PAGE_FREE;
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nand_ram_flash_spare[i].bad = NAND_RAM_BLOCK_GOOD;
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}
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/* Bad blocks */
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for (i = 0;
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g_nand_ram_rand_bad_blk_indx[i] != 0 &&
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g_nand_ram_rand_bad_blk_indx[i] < NAND_RAM_N_BLOCKS;
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i++)
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{
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int j;
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for (j = 0; j < NAND_RAM_PAGES_PER_BLOCK; j++)
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{
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int page = (g_nand_ram_rand_bad_blk_indx[i] <<
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NAND_RAM_LOG_PAGES_PER_BLOCK)+j;
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/* Set bad block marker to Anything but NAND_RAM_BLOCK_GOOD */
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nand_ram_flash_spare[page].bad = 0;
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}
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nand_ram_eraseblock
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*
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* Description:
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* Erases a block on the device.
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*
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* Input Parameters:
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* raw: NAND MTD Device raw structure.
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* block: Block number (0 indexing) to erase
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*
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* Returned Value:
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* 0: Successful
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* < 0: Error
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*
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****************************************************************************/
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int nand_ram_eraseblock(FAR struct nand_raw_s *raw, off_t block)
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{
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int i;
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uint32_t start_page;
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uint32_t end_page;
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start_page = block << NAND_RAM_LOG_PAGES_PER_BLOCK;
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end_page = start_page + NAND_RAM_PAGES_PER_BLOCK;
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nxmutex_lock(&nand_ram_dev_mut);
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nand_ram_ins_i++;
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NAND_RAM_LOG(
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"[LOWER %" PRIu64 " | %s] Block %" PRIi32 ", Start Page: %" PRIi32
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", Last Page: %" PRIi32, nand_ram_ins_i, "eraseblock", block, start_page,
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end_page - 1);
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nand_ram_status();
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/* [start_page, end_page) is cleared (all bits are set) */
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memset(nand_ram_flash_data + start_page, 0xff,
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(end_page - start_page) * sizeof(struct nand_ram_data_s));
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for (i = start_page; i < end_page; i++)
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{
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nand_ram_flash_spare[i].n_erase++;
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nand_ram_flash_spare[i].free = NAND_RAM_PAGE_FREE;
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}
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Done\n", nand_ram_ins_i,
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"eraseblock");
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nxmutex_unlock(&nand_ram_dev_mut);
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return OK;
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}
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/****************************************************************************
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* Name: nand_ram_rawread
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*
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* Description:
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* Reads a page from the device.
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*
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* Input Parameters:
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* raw: NAND MTD Device raw structure.
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* block: Block number (0 indexing) to erase
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* page: Page number (0 indexing) in (relative to) that block
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* data: Preallocated memory where the data will be copied to
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* spare: Preallocated memory where the spare data will be copied to
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*
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* Returned Value:
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* 0: Successful
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*
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****************************************************************************/
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int nand_ram_rawread(FAR struct nand_raw_s *raw, off_t block,
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unsigned int page, FAR void *data, FAR void *spare)
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{
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int ret;
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uint32_t read_page;
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struct nand_ram_data_s *read_page_data;
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struct nand_ram_spare_s *read_page_spare;
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ret = OK;
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read_page = (block << NAND_RAM_LOG_PAGES_PER_BLOCK) + page;
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read_page_data = nand_ram_flash_data + read_page;
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read_page_spare = nand_ram_flash_spare + read_page;
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nxmutex_lock(&nand_ram_dev_mut);
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nand_ram_ins_i++;
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Page %" PRIi32 "\n",
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nand_ram_ins_i, "rawread", read_page);
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nand_ram_status();
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if (nand_ram_flash_spare[read_page].bad != NAND_RAM_BLOCK_GOOD)
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{
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ret = -EFAULT;
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Failed: %s\n",
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nand_ram_ins_i, "rawread", EFAULT_STR);
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goto errout;
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}
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nand_ram_flash_spare[read_page].n_read++;
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if (data != NULL)
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{
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if (nand_ram_flash_spare[read_page].free == NAND_RAM_PAGE_FREE)
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{
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memset(data, 0, NAND_RAM_PAGE_SIZE);
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}
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else
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{
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memcpy(data, (const void *)read_page_data->page,
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NAND_RAM_PAGE_SIZE);
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}
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}
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if (spare != NULL)
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{
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memcpy(spare, (const void *)read_page_spare, NAND_RAM_SPARE_SIZE);
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}
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Done\n", nand_ram_ins_i, "rawread");
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errout:
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nxmutex_unlock(&nand_ram_dev_mut);
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return ret;
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}
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/****************************************************************************
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* Name: nand_ram_rawread
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*
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* Description:
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* Writes a page to the device.
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*
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* Input Parameters:
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* raw: NAND MTD Device raw structure.
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* block: Block number (0 indexing) to erase
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* page: Page number (0 indexing) in (relative to) that block
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* data: Preallocated memory where the data will be copied to
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* spare: Preallocated memory where the spare data will be copied to
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*
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* Returned Value:
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* 0: Successful
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* -EACCESS: The page's block needs to be erased first before writing to it
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*
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****************************************************************************/
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int nand_ram_rawwrite(FAR struct nand_raw_s *raw, off_t block,
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unsigned int page, FAR const void *data,
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FAR const void *spare)
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{
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int ret;
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uint32_t write_page;
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struct nand_ram_data_s *write_page_data;
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struct nand_ram_spare_s *write_page_spare;
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ret = OK;
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write_page = (block << NAND_RAM_LOG_PAGES_PER_BLOCK) + page;
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write_page_data = nand_ram_flash_data + write_page;
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write_page_spare = nand_ram_flash_spare + write_page;
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nxmutex_lock(&nand_ram_dev_mut);
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nand_ram_ins_i++;
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Page %" PRIi32 "\n",
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nand_ram_ins_i, "rawwrite", write_page);
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nand_ram_status();
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if (nand_ram_flash_spare[write_page].free != NAND_RAM_PAGE_FREE)
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{
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ret = -EACCES;
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Failed: %s\n",
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nand_ram_ins_i, "rawwrite", EACCES_STR);
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goto errout;
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}
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nand_ram_flash_spare[write_page].n_write++;
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nand_ram_flash_spare[write_page].free = NAND_RAM_PAGE_WRITTEN;
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memset((FAR void *)write_page_data->page, 0, NAND_RAM_PAGE_SIZE);
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if (data != NULL)
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{
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memcpy((FAR void *)write_page_data->page, data, NAND_RAM_PAGE_SIZE);
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}
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if (spare != NULL)
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{
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memcpy((FAR void *)write_page_spare, data, NAND_RAM_SPARE_SIZE);
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}
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NAND_RAM_LOG("[LOWER %" PRIu64 " | %s] Done\n", nand_ram_ins_i,
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"rawwrite");
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errout:
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nxmutex_unlock(&nand_ram_dev_mut);
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return ret;
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}
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/****************************************************************************
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* Name: nand_ram_init
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*
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* Description:
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* Driver init.
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*
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* Input Parameters:
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* raw: NAND MTD Device raw structure.
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*
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* Returned Value:
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* A non-NULL MTD driver instance is returned on success. NULL is
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* returned on any failure.
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*
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****************************************************************************/
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FAR struct mtd_dev_s *nand_ram_initialize(struct nand_raw_s *raw)
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{
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NAND_RAM_LOG("[LOWER | %s]\n", "initialize");
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nand_ram_storage_init();
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nxmutex_init(&nand_ram_dev_mut);
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raw->model.devid = 123;
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raw->model.pagesize = NAND_RAM_PAGE_SIZE;
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raw->model.sparesize = NAND_RAM_SPARE_SIZE;
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raw->model.devsize = NAND_RAM_SIZE / (1024 * 1024);
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raw->model.blocksize = NAND_RAM_BLOCK_SIZE / 1024;
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raw->model.scheme = &g_nand_sparescheme512;
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raw->eraseblock = nand_ram_eraseblock;
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raw->rawread = nand_ram_rawread;
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raw->rawwrite = nand_ram_rawwrite;
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return nand_raw_initialize(raw);
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}
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