fc46135ebc
Improvements in STM32 ADC, minor changes in STM32 PWM, DMA, HRTIM and add some highpri ADC examples arch/arch/src/stm32/stm32_adc: fix RCC reset logic arch/arch/src/stm32/stm32_adc: move sample time change functions to low-level ADC ops arch/arch/src/stm32/stm32_adc: configurable ADC DMA mode (one shot mode, circular mode) arch/arch/src/stm32/stm32_pwm: remove llops_get interface. We can use structure casting to get pwm low-level ops arch/arch/src/stm32/stm32_pwm: add timer enable/disable and frequency update to low-level ops arch/src/arm/stm32: remove redundant stm32f33xxx_dma.c arch/arm/src/stm32/stm32f40xxx_dma.c: add interfaces to interact with highp priority DMA interupts arch/src/arm/stm32/stm32_hrtim: do not enable timers on startup if option from Kconfig selected and add interface to enable/disable timers arch/src/arm/stm32/stm32_hrtim: fix some warnings configs/nucleo-f334r8/highpri: update configuration due to changes in stm32_adc configs/stm32f334-disco/buckboost: update configuration due to changes in stm32_adc configs/nucleo-f334r8/highpri: add support for ADC injected sequence, add triggering from TIM1 configs/nucleo-f302r8/highpri: add high priority ADC interrupts example configs/stm32f429i-disco/highpri: add high priority ADC interrupts example Approved-by: GregoryN <gnutt@nuttx.org>
133 lines
3.9 KiB
Plaintext
133 lines
3.9 KiB
Plaintext
/****************************************************************************
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* configs/stm32f429i-disco/scripts/ld.script
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*
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Modified 11/4/2013 for STM32F429 support
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and
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* 256Kb of SRAM. SRAM is split up into four blocks:
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*
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* 1) 112Kb of SRAM beginning at address 0x2000:0000
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* 2) 16Kb of SRAM beginning at address 0x2001:c000
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* 3) 64Kb of SRAM beginning at address 0x2002:0000
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* 4) 64Kb of CCM SRAM beginning at address 0x1000:0000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address
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* range.
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*/
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MEMORY
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{
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flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
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}
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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ENTRY(_stext)
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SECTIONS
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{
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.text : {
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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.init_section : {
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_sinit = ABSOLUTE(.);
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*(.init_array .init_array.*)
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_einit = ABSOLUTE(.);
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} > flash
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.ARM.extab : {
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*(.ARM.extab*)
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} > flash
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__exidx_start = ABSOLUTE(.);
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.ARM.exidx : {
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*(.ARM.exidx*)
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} > flash
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__exidx_end = ABSOLUTE(.);
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_eronly = ABSOLUTE(.);
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/* The RAM vector table (if present) should lie at the beginning of SRAM */
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.ram_vectors : {
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*(.ram_vectors)
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} > sram
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.data : {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.bss : {
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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_ebss = ABSOLUTE(.);
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} > sram
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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}
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