078a0486f5
In SMP mode, if all cores start at same time, all from __start(), then only primary need do initialize, so others core should wait primary, use 'sev' let the non-primary continue to __cpuN_start(). Signed-off-by: ligd <liguiding1@xiaomi.com>
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-a/arm_scu.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "arm_internal.h"
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#include "cp15_cacheops.h"
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#include "barriers.h"
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#include "sctlr.h"
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#include "scu.h"
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#include "cp15.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_enable_smp
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*
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* Description:
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* Enable the SCU and make certain that current CPU is participating in
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* the SMP cache coherency.
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*
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* Assumption:
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* Called early in the CPU start-up. No special critical sections are
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* needed if only CPU-private registers are modified.
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*
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****************************************************************************/
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void arm_enable_smp(int cpu)
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{
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uint32_t regval;
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/* Handle actions unique to CPU0 which comes up first */
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if (cpu == 0)
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{
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/* Invalidate the SCU duplicate tags for all processors */
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putreg32((SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU0_SHIFT) |
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(SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU1_SHIFT) |
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(SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU2_SHIFT) |
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(SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU3_SHIFT),
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SCU_INVALIDATE);
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/* Invalidate CPUn L1 data cache so that is will we be reloaded from
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* coherent L2.
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*/
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cp15_invalidate_dcache_all();
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ARM_DSB();
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/* Invalidate the L2C-310 -- Missing logic. */
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/* Enable the SCU */
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regval = getreg32(SCU_CTRL);
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regval |= SCU_CTRL_ENABLE;
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putreg32(regval, SCU_CTRL);
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/* Initialize done, kick other cpus which waiting on __start */
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ARM_SEV();
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}
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/* Actions for other CPUs */
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else
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{
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/* Invalidate CPUn L1 data cache so that is will we be reloaded from
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* coherent L2.
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*/
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cp15_dcache_op_level(0, CP15_CACHE_INVALIDATE);
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ARM_DSB();
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/* Wait for the SCU to be enabled by the primary processor -- should
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* not be necessary.
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*/
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}
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/* Enable the data cache, set the SMP mode with ACTLR.SMP=1.
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*
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* SMP - Sgnals if the Cortex-A9 processor is taking part in coherency
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* or not.
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*
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* Cortex-A9 also needs ACTLR.FW=1
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*
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* FW - Cache and TLB maintenance broadcast.
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*/
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regval = CP15_GET(ACTLR);
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regval |= ACTLR_SMP;
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#ifdef CONFIG_ARCH_CORTEXA9
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regval |= ACTLR_FW;
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#endif
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CP15_SET(ACTLR, regval);
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regval = CP15_GET(SCTLR);
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regval |= SCTLR_C | SCTLR_I | SCTLR_M;
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CP15_SET(SCTLR, regval);
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}
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