104 lines
4.0 KiB
C
104 lines
4.0 KiB
C
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/****************************************************************************
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* arch/arm/include/stm32wl5/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32WL5_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32WL5_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define STM32WL5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define STM32WL5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define STM32WL5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define STM32WL5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define STM32WL5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define STM32WL5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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/* Vectors 7-10: Reserved */
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#define STM32WL5_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define STM32WL5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define STM32WL5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define STM32WL5_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are
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* chip-specific
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*/
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#define STM32WL5_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
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# include <arch/stm32wl5/stm32wl5xxx_cpu1_irq.h>
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#else
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# error "Unsupported STM32 L5 chip"
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32WL5_IRQ_H */
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