2020-04-09 12:59:57 +02:00
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/****************************************************************************
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2021-03-08 22:39:04 +01:00
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* boards/arm/stm32/nucleo-f429zi/include/board.h
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2020-04-09 12:59:57 +02:00
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Do not include STM32 F4 header files here */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The STM32F4 Discovery board features a single 8MHz crystal. Space is
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* provided for a 32kHz RTC backup crystal, but it is not stuffed.
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*
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* This is the canonical configuration:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 180000000 Determined by PLL config
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* HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage : Scale1 mode Needed for highspeed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (8,000,000 / 8) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* DMA Channel/Stream Selections ********************************************/
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/* Stream selections are arbitrary for now but might become important in the
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* future if we set aside more DMA channels/streams.
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*
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* SDMMC DMA is on DMA2
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*
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* SDMMC1 DMA
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* DMAMAP_SDMMC1_1 = Channel 4, Stream 3
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* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
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*
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* SDMMC2 DMA
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* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
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* DMAMAP_SDMMC3_2 = Channel 11, Stream 5
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*/
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#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1
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#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* LED definitions **********************************************************/
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/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
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* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
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* The following definitions assume the default Solder Bridges are installed.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_BLUE BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode
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* OS-related events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ---
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions *******************************************************/
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/* The STM32F4 Discovery supports one button: Pushbutton B1, labeled "User",
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* is connected to GPIO PI11.
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* A high value will be sensed when the button is depressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* TIM */
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#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1
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#define GPIO_TIM2_CH1OUT GPIO_TIM2_CH1OUT_1
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#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_1
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#define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_1
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#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_ARDUINO)
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/* USART6:
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*
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* These configurations assume that you are using a standard Arduio RS-232
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* shield with the serial interface with RX on pin D0 and TX on pin D1:
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*
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* -------- ---------------
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* STM32F4
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* ARDUIONO FUNCTION GPIO
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* -- ----- --------- -----
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* DO RX USART6_RX PG9
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* D1 TX USART6_TX PG14
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* -- ----- --------- -----
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*/
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# define GPIO_USART6_RX GPIO_USART6_RX_2
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# define GPIO_USART6_TX GPIO_USART6_TX_2
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#endif
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/* USART3:
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* Use USART3 and the USB virtual COM port
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*/
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#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL)
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# define GPIO_USART3_RX GPIO_USART3_RX_3
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# define GPIO_USART3_TX GPIO_USART3_TX_3
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#endif
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/* DMA channels *************************************************************/
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/* ADC */
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#define ADC1_DMA_CHAN DMAMAP_ADC1_1
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#define ADC2_DMA_CHAN DMAMAP_ADC2_1
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#define ADC3_DMA_CHAN DMAMAP_ADC3_1
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/* SPI
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*
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*
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* PA6 SPI1_MISO CN12-13
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* PA7 SPI1_MOSI CN12-15
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* PA5 SPI1_SCK CN12-11
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*
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* PB14 SPI2_MISO CN12-28
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* PB15 SPI2_MOSI CN12-26
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* PB13 SPI2_SCK CN12-30
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*
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* PB4 SPI3_MISO CN12-27
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* PB5 SPI3_MOSI CN12-29
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* PB3 SPI3_SCK CN12-31
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
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/* I2C
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*
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*
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* PB8 I2C1_SCL CN12-3
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* PB9 I2C1_SDA CN12-5
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* PB10 I2C2_SCL CN11-51
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* PB11 I2C2_SDA CN12-18
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*
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* PA8 I2C3_SCL CN12-23
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* PC9 I2C3_SDA CN12-1
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*
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*/
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
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#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
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#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
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/* The STM32 F4 connects to a SMSC LAN8742A PHY using these pins:
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*
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* STM32 F4 BOARD LAN8742A
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* GPIO SIGNAL PIN NAME
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* -------- ------------ -------------
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* PG11 RMII_TX_EN TXEN
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* PG13 RMII_TXD0 TXD0
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* PB13 RMII_TXD1 TXD1
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* PC4 RMII_RXD0 RXD0/MODE0
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* PC5 RMII_RXD1 RXD1/MODE1
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* PG2 RMII_RXER RXER/PHYAD0 -- Not used
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* PA7 RMII_CRS_DV CRS_DV/MODE2
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* PC1 RMII_MDC MDC
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* PA2 RMII_MDIO MDIO
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* N/A NRST nRST
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* PA1 RMII_REF_CLK nINT/REFCLK0
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* N/A OSC_25M XTAL1/CLKIN
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*
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* The PHY address is either 0 or 1, depending on the state of PG2 on reset.
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* PG2 is not controlled but appears to result in a PHY address of 0.
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*/
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1
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#endif /* __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H */
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