2013-04-04 01:47:43 +02:00
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/****************************************************************************
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2019-07-11 18:50:00 +02:00
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* arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c
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2013-04-04 01:47:43 +02:00
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*
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "chip.h"
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2019-07-11 18:50:00 +02:00
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#include "lpc17_40_gpio.h"
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2013-04-04 01:47:43 +02:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Default input pin configuration */
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#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* These tables have global scope because they are also used in
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2019-07-11 18:50:00 +02:00
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* lpc17_40_gpiodbg.c
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2013-04-04 01:47:43 +02:00
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*/
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/* We have to remember the configured interrupt setting.. PINs are not
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* actually set up to interrupt until the interrupt is enabled.
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*/
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2019-07-11 18:50:00 +02:00
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#ifdef CONFIG_LPC17_40_GPIOIRQ
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2013-04-04 01:47:43 +02:00
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uint64_t g_intedge0;
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uint64_t g_intedge2;
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#endif
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/* FIO register base addresses */
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const uint32_t g_fiobase[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_FIO0_BASE,
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LPC17_40_FIO1_BASE,
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LPC17_40_FIO2_BASE,
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LPC17_40_FIO3_BASE,
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LPC17_40_FIO4_BASE
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2013-04-04 01:47:43 +02:00
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#if GPIO_NPORTS > 5
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2019-07-11 18:50:00 +02:00
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, LPC17_40_FIO5_BASE
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2013-04-04 01:47:43 +02:00
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#endif
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};
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/* Port 0 and Port 2 can provide a single interrupt for any combination of
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* port pins
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*/
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const uint32_t g_intbase[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_GPIOINT0_BASE,
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2013-04-04 01:47:43 +02:00
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0,
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2019-07-11 18:50:00 +02:00
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LPC17_40_GPIOINT2_BASE,
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2013-04-04 01:47:43 +02:00
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0,
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0
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_lopinsel[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_PINSEL0,
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LPC17_40_PINCONN_PINSEL2,
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LPC17_40_PINCONN_PINSEL4,
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2013-04-04 01:47:43 +02:00
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0,
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0
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_hipinsel[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_PINSEL1,
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LPC17_40_PINCONN_PINSEL3,
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2013-04-04 01:47:43 +02:00
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0,
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_PINSEL7,
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LPC17_40_PINCONN_PINSEL9
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2013-04-04 01:47:43 +02:00
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_lopinmode[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_PINMODE0,
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LPC17_40_PINCONN_PINMODE2,
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LPC17_40_PINCONN_PINMODE4,
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2013-04-04 01:47:43 +02:00
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0,
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0
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_hipinmode[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_PINMODE1,
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LPC17_40_PINCONN_PINMODE3,
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2013-04-04 01:47:43 +02:00
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0,
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_PINMODE7,
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LPC17_40_PINCONN_PINMODE9
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2013-04-04 01:47:43 +02:00
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_odmode[GPIO_NPORTS] =
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{
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2019-07-11 18:50:00 +02:00
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LPC17_40_PINCONN_ODMODE0,
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LPC17_40_PINCONN_ODMODE1,
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LPC17_40_PINCONN_ODMODE2,
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LPC17_40_PINCONN_ODMODE3,
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LPC17_40_PINCONN_ODMODE4
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2013-04-04 01:47:43 +02:00
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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2019-07-11 18:50:00 +02:00
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* Name: lpc17_40_pinsel
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2013-04-04 01:47:43 +02:00
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*
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* Description:
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* Get the address of the PINSEL register corresponding to this port and
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* pin number.
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*
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****************************************************************************/
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2019-07-11 18:50:00 +02:00
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static int lpc17_40_pinsel(unsigned int port, unsigned int pin, unsigned int value)
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2013-04-04 01:47:43 +02:00
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{
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const uint32_t *table;
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uint32_t regaddr;
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uint32_t regval;
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unsigned int shift;
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/* Which table do we use */
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if (pin < 16)
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{
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table = g_lopinsel;
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shift = PINCONN_PINSELL_SHIFT(pin);
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}
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else
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{
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table = g_hipinsel;
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shift = PINCONN_PINSELH_SHIFT(pin);
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}
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/* Fetch the PINSEL register address for this port/pin combination */
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regaddr = table[port];
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if (regaddr != 0)
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{
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/* Set the requested value in the PINSEL register */
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regval = getreg32(regaddr);
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regval &= ~(PINCONN_PINSEL_MASK << shift);
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regval |= (value << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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2019-07-11 18:50:00 +02:00
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* Name: lpc17_40_pullup
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2013-04-04 01:47:43 +02:00
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*
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* Description:
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* Get the address of the PINMODE register corresponding to this port and
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* pin number.
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*
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****************************************************************************/
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2019-07-11 18:50:00 +02:00
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static int lpc17_40_pullup(lpc17_40_pinset_t cfgset, unsigned int port,
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2013-04-04 01:47:43 +02:00
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unsigned int pin)
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{
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const uint32_t *table;
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uint32_t regaddr;
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uint32_t regval;
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uint32_t value;
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unsigned int shift;
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switch (cfgset & GPIO_PUMODE_MASK)
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{
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default:
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case GPIO_PULLUP: /* Pull-up resistor enabled */
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value = PINCONN_PINMODE_PU;
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break;
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case GPIO_REPEATER: /* Repeater mode enabled */
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value = PINCONN_PINMODE_RM;
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break;
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case GPIO_FLOAT: /* Neither pull-up nor -down */
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value = PINCONN_PINMODE_FLOAT;
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break;
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case GPIO_PULLDN: /* Pull-down resistor enabled */
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value = PINCONN_PINMODE_PD;
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break;
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}
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/* Which table do we use */
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if (pin < 16)
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{
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table = g_lopinmode;
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shift = PINCONN_PINMODEL_SHIFT(pin);
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}
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else
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{
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table = g_hipinmode;
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shift = PINCONN_PINMODEH_SHIFT(pin);
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}
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/* Fetch the PINSEL register address for this port/pin combination */
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regaddr = table[port];
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if (regaddr != 0)
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{
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/* Set the requested value in the PINSEL register */
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regval = getreg32(regaddr);
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regval &= ~(PINCONN_PINMODE_MASK << shift);
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regval |= (value << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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2019-07-11 18:50:00 +02:00
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* Name: lpc17_40_setintedge
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2013-04-04 01:47:43 +02:00
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*
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* Description:
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* Remember the configured interrupt edge. We can't actually enable the
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* the edge interrupts until the called calls IRQ enabled function.
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*
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****************************************************************************/
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2019-07-11 18:50:00 +02:00
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#ifdef CONFIG_LPC17_40_GPIOIRQ
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static void lpc17_40_setintedge(unsigned int port, unsigned int pin,
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2013-04-04 01:47:43 +02:00
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unsigned int value)
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{
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uint64_t *intedge;
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unsigned int shift;
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/* Which word to we use? */
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if (port == 0)
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{
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intedge = &g_intedge0;
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}
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else if (port == 2)
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{
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intedge = &g_intedge2;
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}
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else
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{
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return;
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}
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/* Set the requested value in the PINSEL register */
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shift = pin << 1;
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*intedge &= ~((uint64_t)3 << shift);
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*intedge |= ((uint64_t)value << shift);
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}
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2019-07-11 18:50:00 +02:00
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#endif /* CONFIG_LPC17_40_GPIOIRQ */
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2013-04-04 01:47:43 +02:00
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/****************************************************************************
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2019-07-11 18:50:00 +02:00
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* Name: lpc17_40_setopendrain
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2013-04-04 01:47:43 +02:00
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*
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* Description:
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* Set the ODMODE register for open drain mode
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*
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****************************************************************************/
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2019-07-11 18:50:00 +02:00
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static void lpc17_40_setopendrain(unsigned int port, unsigned int pin)
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2013-04-04 01:47:43 +02:00
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{
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uint32_t regaddr;
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uint32_t regval;
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regaddr = g_odmode[port];
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regval = getreg32(regaddr);
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regval |= (1 << pin);
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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2019-07-11 18:50:00 +02:00
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* Name: lpc17_40_clropendrain
|
2013-04-04 01:47:43 +02:00
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*
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* Description:
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* Reset the ODMODE register to disable open drain mode
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*
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****************************************************************************/
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|
2019-07-11 18:50:00 +02:00
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static void lpc17_40_clropendrain(unsigned int port, unsigned int pin)
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2013-04-04 01:47:43 +02:00
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{
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uint32_t regaddr;
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uint32_t regval;
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regaddr = g_odmode[port];
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regval = getreg32(regaddr);
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regval &= ~(1 << pin);
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putreg32(regval, regaddr);
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}
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|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_configinput
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure a GPIO inpue pin based on bit-encoded description of the pin.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
static inline int lpc17_40_configinput(lpc17_40_pinset_t cfgset, unsigned int port, unsigned int pin)
|
2013-04-04 01:47:43 +02:00
|
|
|
{
|
|
|
|
uint32_t regval;
|
|
|
|
uint32_t fiobase;
|
|
|
|
uint32_t intbase;
|
|
|
|
uint32_t pinmask = (1 << pin);
|
|
|
|
|
|
|
|
/* Set up FIO registers */
|
|
|
|
|
|
|
|
fiobase = g_fiobase[port];
|
|
|
|
|
|
|
|
/* Set as input */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
regval = getreg32(fiobase + LPC17_40_FIO_DIR_OFFSET);
|
2013-04-04 01:47:43 +02:00
|
|
|
regval &= ~pinmask;
|
2019-07-11 18:50:00 +02:00
|
|
|
putreg32(regval, fiobase + LPC17_40_FIO_DIR_OFFSET);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Set up interrupt registers */
|
|
|
|
|
|
|
|
intbase = g_intbase[port];
|
|
|
|
if (intbase != 0)
|
|
|
|
{
|
|
|
|
/* Disable any rising edge interrupts */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
regval = getreg32(intbase + LPC17_40_GPIOINT_INTENR_OFFSET);
|
2013-04-04 01:47:43 +02:00
|
|
|
regval &= ~pinmask;
|
2019-07-11 18:50:00 +02:00
|
|
|
putreg32(regval, intbase + LPC17_40_GPIOINT_INTENR_OFFSET);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Disable any falling edge interrupts */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
regval = getreg32(intbase + LPC17_40_GPIOINT_INTENF_OFFSET);
|
2013-04-04 01:47:43 +02:00
|
|
|
regval &= ~pinmask;
|
2019-07-11 18:50:00 +02:00
|
|
|
putreg32(regval, intbase + LPC17_40_GPIOINT_INTENF_OFFSET);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Forget about any falling/rising edge interrupt enabled */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
#ifdef CONFIG_LPC17_40_GPIOIRQ
|
|
|
|
lpc17_40_setintedge(port, pin, 0);
|
2013-04-04 01:47:43 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set up PINSEL registers */
|
|
|
|
/* Configure as GPIO */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_pinsel(port, pin, PINCONN_PINSEL_GPIO);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Set pull-up mode */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_pullup(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Open drain only applies to outputs */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_clropendrain(port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_configinterrupt
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure a GPIO interrupt pin based on bit-encoded description of the pin.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
static inline int lpc17_40_configinterrupt(lpc17_40_pinset_t cfgset, unsigned int port,
|
2013-04-04 01:47:43 +02:00
|
|
|
unsigned int pin)
|
|
|
|
{
|
|
|
|
/* First, configure the port as a generic input so that we have a known
|
|
|
|
* starting point and consistent behavior during the re-configuration.
|
|
|
|
*/
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
lpc17_40_configinput(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Then just remember the rising/falling edge interrupt enabled */
|
|
|
|
|
|
|
|
DEBUGASSERT(port == 0 || port == 2);
|
2019-07-11 18:50:00 +02:00
|
|
|
#ifdef CONFIG_LPC17_40_GPIOIRQ
|
|
|
|
lpc17_40_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
|
2013-04-04 01:47:43 +02:00
|
|
|
#endif
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_configoutput
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure a GPIO output pin based on bit-encoded description of the pin.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
static inline int lpc17_40_configoutput(lpc17_40_pinset_t cfgset, unsigned int port,
|
2013-04-04 01:47:43 +02:00
|
|
|
unsigned int pin)
|
|
|
|
{
|
|
|
|
uint32_t fiobase;
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
/* First, configure the port as a generic input so that we have a known
|
|
|
|
* starting point and consistent behavior during the re-configuration.
|
|
|
|
*/
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
lpc17_40_configinput(DEFAULT_INPUT, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Check for open drain output */
|
|
|
|
|
|
|
|
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
|
|
|
{
|
|
|
|
/* Set pull-up mode. This normally only applies to input pins, but does have
|
|
|
|
* meaning if the port is an open drain output.
|
|
|
|
*/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_pullup(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Select open drain output */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_setopendrain(port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Set the initial value of the output */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO));
|
2013-04-04 01:47:43 +02:00
|
|
|
|
2015-05-02 14:30:19 +02:00
|
|
|
/* Now, reconfigure the pin as an output */
|
|
|
|
|
|
|
|
fiobase = g_fiobase[port];
|
2019-07-11 18:50:00 +02:00
|
|
|
regval = getreg32(fiobase + LPC17_40_FIO_DIR_OFFSET);
|
2015-05-02 14:30:19 +02:00
|
|
|
regval |= (1 << pin);
|
2019-07-11 18:50:00 +02:00
|
|
|
putreg32(regval, fiobase + LPC17_40_FIO_DIR_OFFSET);
|
2015-05-02 14:30:19 +02:00
|
|
|
|
|
|
|
|
2013-04-04 01:47:43 +02:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_configalternate
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure a GPIO alternate function pin based on bit-encoded description
|
|
|
|
* of the pin.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
static int lpc17_40_configalternate(lpc17_40_pinset_t cfgset, unsigned int port,
|
2013-04-04 01:47:43 +02:00
|
|
|
unsigned int pin, uint32_t alt)
|
|
|
|
{
|
|
|
|
/* First, configure the port as an input so that we have a known
|
|
|
|
* starting point and consistent behavior during the re-configuration.
|
|
|
|
*/
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
lpc17_40_configinput(DEFAULT_INPUT, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Set up PINSEL registers */
|
|
|
|
/* Configure as GPIO */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_pinsel(port, pin, alt);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Set pull-up mode */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_pullup(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
|
|
|
|
/* Check for open drain output */
|
|
|
|
|
|
|
|
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
|
|
|
{
|
|
|
|
/* Select open drain output */
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
lpc17_40_setopendrain(port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2015-10-03 01:42:29 +02:00
|
|
|
* Public Functions
|
2013-04-04 01:47:43 +02:00
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_configgpio
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure a GPIO pin based on bit-encoded description of the pin.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
int lpc17_40_configgpio(lpc17_40_pinset_t cfgset)
|
2013-04-04 01:47:43 +02:00
|
|
|
{
|
|
|
|
unsigned int port;
|
|
|
|
unsigned int pin;
|
|
|
|
int ret = -EINVAL;
|
|
|
|
|
|
|
|
/* Verify that this hardware supports the select GPIO port */
|
|
|
|
|
|
|
|
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
|
|
|
if (port < GPIO_NPORTS)
|
|
|
|
{
|
|
|
|
/* Get the pin number and select the port configuration register for that pin */
|
|
|
|
|
|
|
|
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
|
|
|
|
|
|
|
/* Handle according to pin function */
|
|
|
|
|
|
|
|
switch (cfgset & GPIO_FUNC_MASK)
|
|
|
|
{
|
|
|
|
case GPIO_INPUT: /* GPIO input pin */
|
2019-07-11 18:50:00 +02:00
|
|
|
ret = lpc17_40_configinput(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
|
|
|
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
|
|
|
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
2019-07-11 18:50:00 +02:00
|
|
|
ret = lpc17_40_configinterrupt(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_OUTPUT: /* GPIO outpout pin */
|
2019-07-11 18:50:00 +02:00
|
|
|
ret = lpc17_40_configoutput(cfgset, port, pin);
|
2013-04-04 01:47:43 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_ALT1: /* Alternate function 1 */
|
2019-07-11 18:50:00 +02:00
|
|
|
ret = lpc17_40_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1);
|
2013-04-04 01:47:43 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_ALT2: /* Alternate function 2 */
|
2019-07-11 18:50:00 +02:00
|
|
|
ret = lpc17_40_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2);
|
2013-04-04 01:47:43 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_ALT3: /* Alternate function 3 */
|
2019-07-11 18:50:00 +02:00
|
|
|
ret = lpc17_40_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3);
|
2013-04-04 01:47:43 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_gpiowrite
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Write one or zero to the selected GPIO pin
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
void lpc17_40_gpiowrite(lpc17_40_pinset_t pinset, bool value)
|
2013-04-04 01:47:43 +02:00
|
|
|
{
|
|
|
|
uint32_t fiobase;
|
|
|
|
uint32_t offset;
|
|
|
|
unsigned int port;
|
|
|
|
unsigned int pin;
|
|
|
|
|
|
|
|
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
|
|
|
if (port < GPIO_NPORTS)
|
|
|
|
{
|
|
|
|
/* Get the port base address */
|
|
|
|
|
|
|
|
fiobase = g_fiobase[port];
|
|
|
|
|
|
|
|
/* Get the pin number */
|
|
|
|
|
|
|
|
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
|
|
|
|
|
|
|
/* Set or clear the output on the pin */
|
|
|
|
|
|
|
|
if (value)
|
|
|
|
{
|
2019-07-11 18:50:00 +02:00
|
|
|
offset = LPC17_40_FIO_SET_OFFSET;
|
2013-04-04 01:47:43 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-07-11 18:50:00 +02:00
|
|
|
offset = LPC17_40_FIO_CLR_OFFSET;
|
2013-04-04 01:47:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
putreg32((1 << pin), fiobase + offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_gpioread
|
2013-04-04 01:47:43 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Read one or zero from the selected GPIO pin
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
bool lpc17_40_gpioread(lpc17_40_pinset_t pinset)
|
2013-04-04 01:47:43 +02:00
|
|
|
{
|
|
|
|
uint32_t fiobase;
|
|
|
|
unsigned int port;
|
|
|
|
unsigned int pin;
|
|
|
|
|
|
|
|
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
|
|
|
if (port < GPIO_NPORTS)
|
|
|
|
{
|
|
|
|
/* Get the port base address */
|
|
|
|
|
|
|
|
fiobase = g_fiobase[port];
|
|
|
|
|
|
|
|
/* Get the pin number and return the input state of that pin */
|
|
|
|
|
|
|
|
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
2019-07-11 18:50:00 +02:00
|
|
|
return ((getreg32(fiobase + LPC17_40_FIO_PIN_OFFSET) & (1 << pin)) != 0);
|
2013-04-04 01:47:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|