2023-01-26 00:18:20 +01:00
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/****************************************************************************
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* boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F777ZIT6_MEADOW_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F777ZIT6_MEADOW_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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2023-05-13 10:33:29 +02:00
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# include <stdint.h>
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2023-01-26 00:18:20 +01:00
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#endif
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/* Do not include STM32F7 header files here */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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2023-07-17 22:19:00 +02:00
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/* The Meadow board provides the following clock sources:
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2023-01-26 00:18:20 +01:00
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*
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* X2: 25 MHz oscillator for STM32F777ZIT6 microcontroller
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* and Ethernet PHY.
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* X1: 32.768 KHz crystal for STM32F777ZIT6 embedded RTC
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: On-board crystal frequency is 25MHz
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* LSE: 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 25000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 25,000,000
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*
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 2 <= PLLM <= 63
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* 192 <= PLLN <= 432
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* 192 MHz <= PLL_VCO <= 432MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* Subject to
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*
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* PLLP = {2, 4, 6, 8}
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* SYSCLK <= 216 MHz
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*
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* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
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* Subject to
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* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
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* and the random number generator need a frequency lower than or equal
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* to 48 MHz to work correctly.
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*
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* 2 <= PLLQ <= 15
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*/
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#if defined(CONFIG_STM32F7_OTGFS)
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/* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz
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*
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* PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz
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* SYSCLK = 384 MHz / 2 = 192 MHz
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* USB OTG FS, SDMMC and RNG Clock = 384 MHz / 8 = 48MHz
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* DSI CLK = PLL_VCO / PLLR = 384 / 7 = 54,86 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(7)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 384)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8)
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#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG)
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/* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz
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*
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* PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
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* DSI CLK = PLL_VCO / PLLR = 432 / 8 = 54 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(8)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#else
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/* No restrictions by OTGFS
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*
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* PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
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* DSI CLK = PLL_VCO / PLLR = 432 / 8 = 54 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(8)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#endif
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/* Configure factors for PLLSAI clock */
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2023-07-17 22:19:00 +02:00
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#define CONFIG_STM32F7_PLLSAI 1
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(384)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
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/* Configure factors for PLLI2S clock */
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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/* Configure Dedicated Clock Configuration Register 2 */
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#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
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#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
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#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
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#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
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#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
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#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
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#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
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#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
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#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
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#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
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#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
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#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
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#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
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#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
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/* Several prescalers allow the configuration of the two AHB buses, the
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
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* the low-speed APB domain is 54 MHz.
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*/
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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#define BOARD_AHB_FREQUENCY STM32_HCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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2023-05-10 20:45:11 +02:00
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
|
|
|
|
|
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_DMA
|
|
|
|
|
# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
|
|
|
|
#else
|
|
|
|
|
# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
|
|
|
|
|
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_DMA
|
|
|
|
|
# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
|
|
|
|
#else
|
|
|
|
|
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
|
|
|
|
#endif
|
|
|
|
|
|
2023-01-26 00:18:20 +01:00
|
|
|
/* LED definitions **********************************************************/
|
|
|
|
|
|
|
|
|
|
/* The STM32F777ZIT6-MEADOW board has numerous LEDs but only one, LD1
|
|
|
|
|
* located near the reset button, that can be controlled by software
|
|
|
|
|
* (LD2 is a power indicator, LD3-6
|
|
|
|
|
* indicate USB status, LD7 is controlled by the ST-Link).
|
|
|
|
|
*
|
|
|
|
|
* LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino
|
|
|
|
|
* interface.
|
|
|
|
|
* One end of LD1 is grounded so a high output on PI1 will illuminate
|
|
|
|
|
* the LED.
|
|
|
|
|
*
|
|
|
|
|
* If CONFIG_ARCH_LEDS is not defined, then the user can control the
|
|
|
|
|
* LEDs in any way.
|
|
|
|
|
* The following definitions are used to access individual LEDs.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* LED index values for use with board_userled() */
|
|
|
|
|
|
|
|
|
|
#define BOARD_LED1 0
|
|
|
|
|
#define BOARD_LED2 1
|
|
|
|
|
#define BOARD_LED3 2
|
|
|
|
|
#define BOARD_NLEDS 3
|
|
|
|
|
|
|
|
|
|
#define BOARD_LED_GREEN BOARD_LED1
|
|
|
|
|
#define BOARD_LED_BLUE BOARD_LED2
|
|
|
|
|
#define BOARD_LED_RED BOARD_LED3
|
|
|
|
|
|
|
|
|
|
/* LED bits for use with board_userled_all() */
|
|
|
|
|
|
|
|
|
|
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
|
|
|
|
#define BOARD_LED2_BIT (1 << BOARD_LED2)
|
|
|
|
|
#define BOARD_LED3_BIT (1 << BOARD_LED3)
|
|
|
|
|
|
|
|
|
|
/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
|
2023-07-11 14:36:33 +02:00
|
|
|
* include/board.h and src/stm32_leds.c. The LEDs are used
|
2023-01-26 00:18:20 +01:00
|
|
|
* to encode OS-related events as follows:
|
|
|
|
|
*
|
|
|
|
|
* SYMBOL Meaning LD1
|
|
|
|
|
* ------------------- ----------------------- ------
|
|
|
|
|
* LED_STARTED NuttX has been started OFF
|
|
|
|
|
* LED_HEAPALLOCATE Heap has been allocated OFF
|
|
|
|
|
* LED_IRQSENABLED Interrupts enabled OFF
|
|
|
|
|
* LED_STACKCREATED Idle stack created ON
|
|
|
|
|
* LED_INIRQ In an interrupt N/C
|
|
|
|
|
* LED_SIGNAL In a signal handler N/C
|
|
|
|
|
* LED_ASSERTION An assertion failed N/C
|
|
|
|
|
* LED_PANIC The system has crashed FLASH
|
|
|
|
|
*
|
|
|
|
|
* Thus is LD1 is statically on, NuttX has successfully booted and is,
|
|
|
|
|
* apparently, running normally. If LD1 is flashing at approximately
|
|
|
|
|
* 2Hz, then a fatal error has been detected and the system has halted.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
|
|
|
|
|
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
|
|
|
|
|
#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
|
|
|
|
|
#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
|
|
|
|
|
#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
|
|
|
|
|
#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
|
|
|
|
|
#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
|
|
|
|
|
#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
|
|
|
|
|
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
|
|
|
|
|
|
|
|
|
|
/* Button definitions *******************************************************/
|
|
|
|
|
|
|
|
|
|
/* The STM32F7 Discovery supports one button:
|
|
|
|
|
* Pushbutton B1, labelled "User", is connected to GPIO PA0.
|
|
|
|
|
* A high value will be sensed when the button is depressed.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define BUTTON_USER 0
|
|
|
|
|
#define NUM_BUTTONS 1
|
|
|
|
|
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
|
|
|
|
|
2023-05-10 20:45:11 +02:00
|
|
|
/* LED definitions **********************************************************/
|
|
|
|
|
|
|
|
|
|
/* LCD DISPLAY
|
|
|
|
|
* (work in progress as of 2017 07 19)
|
|
|
|
|
*/
|
|
|
|
|
|
2023-07-11 14:36:33 +02:00
|
|
|
#define BOARD_LTDC_WIDTH 800
|
|
|
|
|
#define BOARD_LTDC_HEIGHT 472
|
2023-05-10 20:45:11 +02:00
|
|
|
|
2023-07-11 14:36:33 +02:00
|
|
|
#define BOARD_LTDC_HSYNC 10
|
|
|
|
|
#define BOARD_LTDC_HFP 10
|
|
|
|
|
#define BOARD_LTDC_HBP 20
|
|
|
|
|
#define BOARD_LTDC_VSYNC 2
|
|
|
|
|
#define BOARD_LTDC_VFP 4
|
|
|
|
|
#define BOARD_LTDC_VBP 2
|
2023-05-10 20:45:11 +02:00
|
|
|
|
2023-07-11 14:36:33 +02:00
|
|
|
#define BOARD_LTDC_GCR_PCPOL 0
|
|
|
|
|
#define BOARD_LTDC_GCR_DEPOL 0
|
|
|
|
|
#define BOARD_LTDC_GCR_VSPOL 0
|
|
|
|
|
#define BOARD_LTDC_GCR_HSPOL 0
|
2023-05-10 20:45:11 +02:00
|
|
|
|
|
|
|
|
/* DMA Channel/Stream Selections ********************************************/
|
|
|
|
|
|
|
|
|
|
/* SDMMC */
|
|
|
|
|
|
|
|
|
|
/* Stream selections are arbitrary for now but might become important in the
|
|
|
|
|
* future if we set aside more DMA channels/streams.
|
|
|
|
|
*
|
|
|
|
|
* SDIO DMA
|
|
|
|
|
* DMAMAP_SDMMC1_1 = Channel 4, Stream 3
|
|
|
|
|
* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
|
|
|
|
|
*
|
|
|
|
|
* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
|
|
|
|
|
* DMAMAP_SDMMC2_2 = Channel 11, Stream 5
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1
|
|
|
|
|
|
2023-01-26 00:18:20 +01:00
|
|
|
/* Alternate function pin selections ****************************************/
|
|
|
|
|
|
|
|
|
|
/* USART6:
|
|
|
|
|
*
|
|
|
|
|
* These configurations assume that you are using a standard Arduio
|
|
|
|
|
* RS-232 shield with the serial interface with RX on pin D0 and TX
|
|
|
|
|
* on pin D1:
|
|
|
|
|
*
|
|
|
|
|
* -------- ---------------
|
|
|
|
|
* STM32F7
|
|
|
|
|
* ARDUINO FUNCTION GPIO
|
|
|
|
|
* -- ----- --------- -----
|
|
|
|
|
* DO RX USART6_RX PC7
|
|
|
|
|
* D1 TX USART6_TX PC6
|
|
|
|
|
* -- ----- --------- -----
|
|
|
|
|
*/
|
|
|
|
|
|
2023-05-10 20:45:11 +02:00
|
|
|
#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz)
|
2023-01-26 00:18:20 +01:00
|
|
|
|
|
|
|
|
/* USART1:
|
|
|
|
|
* USART1 is connected to the "Virtual Com Port" lines
|
|
|
|
|
* of the ST-LINK controller.
|
|
|
|
|
*
|
|
|
|
|
* -------- ---------------
|
|
|
|
|
* STM32F7
|
|
|
|
|
* SIGNAME FUNCTION GPIO
|
|
|
|
|
* -- ----- --------- -----
|
|
|
|
|
* VCP_RX USART1_RX PA10
|
|
|
|
|
* VCP_TX USART1_TX PA9
|
|
|
|
|
* -- ----- --------- -----
|
|
|
|
|
*/
|
|
|
|
|
|
2023-05-10 20:45:11 +02:00
|
|
|
#define GPIO_USART1_RX (GPIO_USART1_RX_3|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_USART1_TX (GPIO_USART1_TX_3|GPIO_SPEED_100MHz)
|
2023-01-26 00:18:20 +01:00
|
|
|
|
|
|
|
|
/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
|
|
|
|
|
*
|
|
|
|
|
* STM32 F7 BOARD LAN8742A
|
|
|
|
|
* GPIO SIGNAL PIN NAME
|
|
|
|
|
* -------- ------------ -------------
|
|
|
|
|
* PG11 RMII_TX_EN TXEN
|
|
|
|
|
* PG13 RMII_TXD0 TXD0
|
|
|
|
|
* PG14 RMII_TXD1 TXD1
|
|
|
|
|
* PC4 RMII_RXD0 RXD0/MODE0
|
|
|
|
|
* PC5 RMII_RXD1 RXD1/MODE1
|
|
|
|
|
* PD5 RMII_RXER RXER/PHYAD0
|
|
|
|
|
* PA7 RMII_CRS_DV CRS_DV/MODE2
|
|
|
|
|
* PC1 RMII_MDC MDC
|
|
|
|
|
* PA2 RMII_MDIO MDIO
|
|
|
|
|
* N/A NRST nRST
|
|
|
|
|
* PA1 RMII_REF_CLK nINT/REFCLK0
|
|
|
|
|
* N/A OSC_25M XTAL1/CLKIN
|
|
|
|
|
*
|
|
|
|
|
* The PHY address is 0, since RMII_RXER/PHYAD0 features a pull down.
|
|
|
|
|
* After reset, RMII_RXER/PHYAD0 switches to the RXER function,
|
|
|
|
|
* receive errors can be detected using GPIO pin PD5
|
|
|
|
|
*/
|
|
|
|
|
|
2023-05-10 20:45:11 +02:00
|
|
|
#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz)
|
2023-01-26 00:18:20 +01:00
|
|
|
|
|
|
|
|
/* I2C Mapping
|
|
|
|
|
* I2C #4 is connected to the LCD daughter board
|
|
|
|
|
* and the WM8994 audio codec.
|
|
|
|
|
*
|
|
|
|
|
* I2C4_SCL - PD12
|
|
|
|
|
* I2C4_SDA - PB7
|
|
|
|
|
*/
|
2023-05-10 20:45:11 +02:00
|
|
|
#define GPIO_I2C4_SCL (GPIO_I2C4_SCL_1|GPIO_SPEED_50MHz)
|
|
|
|
|
#define GPIO_I2C4_SDA (GPIO_I2C4_SDA_5|GPIO_SPEED_50MHz)
|
2023-01-26 00:18:20 +01:00
|
|
|
|
|
|
|
|
/* QSPI Mapping */
|
|
|
|
|
|
|
|
|
|
#define GPIO_QSPI_CS (GPIO_QUADSPI_BK1_NCS_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_QSPI_IO0 (GPIO_QUADSPI_BK1_IO0_3 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_QSPI_IO1 (GPIO_QUADSPI_BK1_IO1_3 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_QSPI_IO2 (GPIO_QUADSPI_BK1_IO2_1 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_QSPI_IO3 (GPIO_QUADSPI_BK1_IO3_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_QSPI_SCK (GPIO_QUADSPI_CLK_1 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
|
|
|
|
|
|
|
|
|
|
/* SDMMC2 Pin mapping
|
|
|
|
|
*
|
|
|
|
|
* D0 - PG9
|
|
|
|
|
* D1 - PG10
|
|
|
|
|
* D2 - PB3
|
|
|
|
|
* D3 - PB4
|
|
|
|
|
*/
|
|
|
|
|
|
2023-05-10 20:45:11 +02:00
|
|
|
#define GPIO_SDMMC2_CK (GPIO_SDMMC2_CK_0|GPIO_SPEED_50MHz)
|
|
|
|
|
#define GPIO_SDMMC2_CMD (GPIO_SDMMC2_CMD_0|GPIO_SPEED_50MHz)
|
|
|
|
|
#define GPIO_SDMMC2_D0 (GPIO_SDMMC2_D0_2|GPIO_SPEED_50MHz)
|
|
|
|
|
#define GPIO_SDMMC2_D1 (GPIO_SDMMC2_D1_2|GPIO_SPEED_50MHz)
|
|
|
|
|
#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz)
|
|
|
|
|
#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz)
|
2023-01-26 00:18:20 +01:00
|
|
|
|
2023-06-17 21:17:42 +02:00
|
|
|
/* OTGFS */
|
|
|
|
|
|
|
|
|
|
#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
|
|
|
|
|
|
2023-05-10 20:45:11 +02:00
|
|
|
/* FMC - SDRAM */
|
2023-01-26 00:18:20 +01:00
|
|
|
|
2023-06-17 21:17:42 +02:00
|
|
|
#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_A12 (GPIO_FMC_A12_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz)
|
|
|
|
|
#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDCKE0 (GPIO_FMC_SDCKE0_3|GPIO_SPEED_100MHz)
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2023-05-10 20:45:11 +02:00
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#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz)
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2023-06-17 21:17:42 +02:00
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#define GPIO_FMC_SDNE0 (GPIO_FMC_SDNE0_3|GPIO_SPEED_100MHz)
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2023-05-10 20:45:11 +02:00
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#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz)
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2023-06-17 21:17:42 +02:00
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#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_3|GPIO_SPEED_100MHz)
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2023-01-26 00:18:20 +01:00
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#endif /* __BOARDS_ARM_STM32F777ZIT6_MEADOW_INCLUDE_BOARD_H */
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