2018-09-04 15:18:12 +02:00
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/****************************************************************************
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* arch/arm/src/stm32f7/stm32_pmstop.c
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*
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2021-11-15 08:16:58 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2018-09-04 15:18:12 +02:00
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*
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2021-11-15 08:16:58 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2018-09-04 15:18:12 +02:00
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*
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2021-11-15 08:16:58 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2018-09-04 15:18:12 +02:00
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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2020-05-01 03:20:29 +02:00
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#include "arm_arch.h"
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2018-09-04 15:18:12 +02:00
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#include "nvic.h"
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#include "stm32_pwr.h"
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#include "stm32_pm.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_pmstop
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*
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* Description:
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* Enter STOP mode.
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*
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* Input Parameters:
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* lpds - true: To further reduce power consumption in Stop mode, put the
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2021-02-26 16:20:54 +01:00
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* internal voltage regulator in low-power under-drive mode using
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* the LPDS and LPUDS bits of the Power control register (PWR_CR1).
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2018-09-04 15:18:12 +02:00
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void stm32_pmstop(bool lpds)
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{
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uint32_t regval;
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/* Clear the Power Down Deep Sleep (PDDS), the Low Power Deep Sleep
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2021-02-26 16:20:54 +01:00
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* (LPDS), Under-Drive Enable in Stop Mode (UDEN), Flash Power Down in
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* Stop Mode (FPDS), Main Regulator in Deepsleep Under-Drive Mode (MRUDS),
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* and Low-power Regulator in Deepsleep Under-Drive Mode (LPUDS) bits in
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2018-09-04 15:18:12 +02:00
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* the power control register.
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*/
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regval = getreg32(STM32_PWR_CR1);
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regval &= ~(PWR_CR1_LPDS | PWR_CR1_PDDS | PWR_CR1_FPDS);
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regval &= ~(PWR_CR1_UDEN_ENABLE | PWR_CR1_MRUDS | PWR_CR1_LPUDS);
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/* Set under-drive enabled with low-power regulator. */
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if (lpds)
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{
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regval |= PWR_CR1_UDEN_ENABLE | PWR_CR1_LPUDS | PWR_CR1_LPDS;
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}
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putreg32(regval, STM32_PWR_CR1);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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regval = getreg32(NVIC_SYSCON);
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regval |= NVIC_SYSCON_SLEEPDEEP;
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putreg32(regval, NVIC_SYSCON);
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/* Sleep until the wakeup interrupt or event occurs */
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#ifdef CONFIG_PM_WFE
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/* Mode: SLEEP + Entry with WFE */
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asm volatile ("wfe");
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#else
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/* Mode: SLEEP + Entry with WFI */
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asm volatile ("wfi");
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#endif
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2021-02-26 16:20:54 +01:00
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/* Clear deep sleep bits, so that MCU does not go into deep sleep in
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* idle.
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*/
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2018-09-04 15:18:12 +02:00
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/* Clear the Power Down Deep Sleep (PDDS), the Low Power Deep Sleep
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2021-02-26 16:20:54 +01:00
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* (LPDS) bits, Under-Drive Enable in Stop Mode (UDEN), Main Regulator
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* in Deepsleep Under-Drive Mode (MRUDS), and Low-power Regulator in
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* Deepsleep Under-Drive Mode (LPUDS) in the power control register.
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2018-09-04 15:18:12 +02:00
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*/
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regval = getreg32(STM32_PWR_CR1);
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regval &= ~(PWR_CR1_LPDS | PWR_CR1_PDDS);
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regval &= ~(PWR_CR1_UDEN_ENABLE | PWR_CR1_MRUDS | PWR_CR1_LPUDS);
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putreg32(regval, STM32_PWR_CR1);
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/* Clear SLEEPDEEP bit of Cortex System Control Register */
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regval = getreg32(NVIC_SYSCON);
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regval &= ~NVIC_SYSCON_SLEEPDEEP;
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putreg32(regval, NVIC_SYSCON);
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}
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