2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2020-03-07 12:36:39 +01:00
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* boards/arm/sama5/sama5d2-xult/include/board.h
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2015-09-05 20:13:12 +02:00
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*
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2021-03-17 18:14:12 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2015-09-05 20:13:12 +02:00
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*
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2021-03-17 18:14:12 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2015-09-05 20:13:12 +02:00
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*
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2021-03-17 18:14:12 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2015-09-05 20:13:12 +02:00
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*
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2015-09-05 20:13:12 +02:00
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2019-08-15 18:19:17 +02:00
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#ifndef __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_H
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2015-09-05 20:13:12 +02:00
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2015-09-05 20:13:12 +02:00
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* Included Files
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2015-09-05 20:13:12 +02:00
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#include <nuttx/config.h>
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2015-09-10 21:06:04 +02:00
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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# include <nuttx/irq.h>
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#endif
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2015-09-05 20:13:12 +02:00
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2019-08-15 18:19:17 +02:00
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/* Clocking *****************************************************************/
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2015-09-05 20:13:12 +02:00
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/* On-board crystal frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_SLOWCLK_FREQUENCY (32768) /* Slow Clock: 32.768KHz */
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2022-05-28 06:14:42 +02:00
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#define BOARD_UPLL_FREQUENCY (480000000) /* USB PLL: 480MHz */
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2015-09-05 20:13:12 +02:00
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2021-03-18 09:57:48 +01:00
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
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* These definitions will configure operational clocking.
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*/
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2015-09-05 20:13:12 +02:00
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#if defined(CONFIG_SAMA5_BOOT_SDRAM)
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2019-08-15 18:19:17 +02:00
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/* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate
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* bootloader.
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2020-07-16 19:31:53 +02:00
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* That bootloader had to have already configured the PLL and SDRAM for
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* proper operation.
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2015-09-05 20:13:12 +02:00
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*
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2019-08-15 18:19:17 +02:00
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* In this case, we don not reconfigure the clocking.
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* Rather, we need to query the register settings to determine the clock
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* frequencies.
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* We can only assume that the Main clock source is the on-board 12MHz
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* crystal.
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2015-09-05 20:13:12 +02:00
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*/
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# include <arch/board/board_sdram.h>
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#elif defined(CONFIG_SAMA5D2XULT_384MHZ)
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2019-08-15 18:19:17 +02:00
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/* OHCI Only.
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* This is an alternative slower configuration that will produce a 48MHz
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* USB clock with the required accuracy using only PLLA.
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* When PPLA is used to clock OHCI, an additional requirement is the
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* PLLACK be a multiple of 48MHz.
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* This setup results in a CPU clock of 384MHz.
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2015-09-05 20:13:12 +02:00
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*
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* This case is only interesting for experimentation.
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*/
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# include <arch/board/board_384mhz.h>
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2020-02-28 19:49:11 +01:00
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#elif defined(CONFIG_SAMA5D2XULT_498MHZ)
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/* This is the configuration results in a CPU clock of 498MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_498mhz.h>
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2015-09-05 20:13:12 +02:00
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#elif defined(CONFIG_SAMA5D2XULT_528MHZ)
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2019-08-15 18:19:17 +02:00
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2015-09-05 20:13:12 +02:00
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/* This is the configuration results in a CPU clock of 528MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_528mhz.h>
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#else /* #elif defined(CONFIG_SAMA5D2XULT_396MHZ) */
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2019-08-15 18:19:17 +02:00
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/* This is the configuration provided in the Atmel example code.
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* This setup results in a CPU clock of 396MHz.
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2015-09-05 20:13:12 +02:00
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_396mhz.h>
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#endif
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2021-03-18 09:57:48 +01:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2022-05-28 06:14:42 +02:00
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/* LCD Interface, Geometry and Timing ***************************************/
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/* This configuration applies only to the TM7000 LCD/Touchscreen module.
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* Other LCDs will require changes.
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*
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* NOTE:
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* The TM7000 user manual claims that the hardware interface is
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* 18-bit RGB666.
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* If you select that, you will get a very pink display (because the
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* upper, "red" bits floating high).
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* By trial and error, the 24-bit select was found to produce the correct
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* color output.
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*
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* NOTE:
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* Timings come from the smaller SAMA5D3x-EK LCD and have not been
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* optimized for this display.
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*/
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#define BOARD_LCDC_OUTPUT_BPP 24 /* Output format is 24 bpp RGB888 */
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#define BOARD_LCDC_WIDTH 800 /* Display width (pixels) */
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#define BOARD_LCDC_HEIGHT 480 /* Display height (rows) */
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#define BOARD_LCDC_MCK_MUL2 1 /* Source clock is 2*Mck (vs Mck) */
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#define BOARD_LCDC_PIXCLK_INV 1 /* Invert pixel clock (falling edge) */
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#define BOARD_LCDC_GUARDTIME 9 /* Guard time (frames) */
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#define BOARD_LCDC_VSPW 2 /* Vertical pulse width (lines) */
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#define BOARD_LCDC_HSPW 128 /* Horizontal pulse width (DOTCLK) */
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#define BOARD_LCDC_VFPW 37 /* Vertical front porch (lines) */
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#define BOARD_LCDC_VBPW 8 /* Vertical back porch (lines) */
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#define BOARD_LCDC_HFPW 168 /* Horizontal front porch (DOTCLK) */
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#define BOARD_LCDC_HBPW 88 /* Horizontal back porch (DOTCLK) */
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/* Pixel clock rate in Hz (HS period * VS period * BOARD_LCDC_FRAMERATE). */
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#define BOARD_LCDC_FRAMERATE 50 /* Frame rate in Hz */
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#define BOARD_LCDC_HSPERIOD \
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(BOARD_LCDC_HSPW + BOARD_LCDC_HBPW + BOARD_LCDC_WIDTH + BOARD_LCDC_HFPW)
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#define BOARD_LCDC_VSPERIOD \
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(BOARD_LCDC_VSPW + BOARD_LCDC_VBPW + BOARD_LCDC_HEIGHT + BOARD_LCDC_VFPW)
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#define BOARD_LCDC_PIXELCLOCK \
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(BOARD_LCDC_HSPERIOD * BOARD_LCDC_VSPERIOD * BOARD_LCDC_FRAMERATE)
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/* Backlight prescaler value and PWM output polarity */
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#define BOARD_LCDC_PWMPS LCDC_LCDCFG6_PWMPS_DIV1
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#define BOARD_LCDC_PWMPOL LCDC_LCDCFG6_PWMPOL
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/* LCDC PIO configuration ***************************************************/
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#define PIO_LCD_DAT2 PIO_LCD_DAT2_2
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#define PIO_LCD_DAT3 PIO_LCD_DAT3_2
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#define PIO_LCD_DAT4 PIO_LCD_DAT4_2
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#define PIO_LCD_DAT5 PIO_LCD_DAT5_2
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#define PIO_LCD_DAT6 PIO_LCD_DAT6_2
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#define PIO_LCD_DAT7 PIO_LCD_DAT7_2
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#define PIO_LCD_DAT10 PIO_LCD_DAT10_2
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#define PIO_LCD_DAT11 PIO_LCD_DAT11_2
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#define PIO_LCD_DAT12 PIO_LCD_DAT12_2
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#define PIO_LCD_DAT13 PIO_LCD_DAT13_2
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#define PIO_LCD_DAT14 PIO_LCD_DAT14_2
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#define PIO_LCD_DAT15 PIO_LCD_DAT15_2
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#define PIO_LCD_DAT18 PIO_LCD_DAT18_2
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#define PIO_LCD_DAT19 PIO_LCD_DAT19_2
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#define PIO_LCD_DAT20 PIO_LCD_DAT20_2
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#define PIO_LCD_DAT21 PIO_LCD_DAT21_2
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#define PIO_LCD_DAT22 PIO_LCD_DAT22_2
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#define PIO_LCD_DAT23 PIO_LCD_DAT23_2
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#define PIO_LCD_DEN PIO_LCD_DEN_2
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#define PIO_LCD_DISP PIO_LCD_DISP_1
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#define PIO_LCD_HSYNC PIO_LCD_HSYNC_1
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#define PIO_LCD_PCK PIO_LCD_PCK_2
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#define PIO_LCD_PWM PIO_LCD_PWM_1
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#define PIO_LCD_VSYNC PIO_LCD_VSYNC_1
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/* Touch screen TWI */
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#define PIO_TWI1_CK (PIO_TWI1_CK_1 | PIO_CFG_PULLUP | \
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PIO_CFG_DEGLITCH | PIO_DRIVE_HIGH)
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#define PIO_TWI1_D (PIO_TWI1_D_1 | PIO_CFG_PULLUP | \
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PIO_CFG_DEGLITCH | PIO_DRIVE_HIGH)
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/* EMAC MII/RMII connection to KSZ8081 Ethernet PHY *************************/
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/* SAMA5D27 Interface KSZ8081 Interface
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* ---- ------------ ------- ----------------------------------
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* PIO Usage Pin Function
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* ---- ------------ ------- ----------------------------------
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* PB9 COL COL Collision Detect Output
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* PB8 CRS CRS Carrier Sense Output
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* PB22 MDC MDC Management Interface Clock Input
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* PB23 MDIO MDIO Management Interface Data I/O
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* PB18 RX0 RX0 Receive Data Output 0
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* PB19 RX1 RX1 Receive Data Output 1
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* PB10 RX2 RX2 Receive Data Output 2
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* PB11 RX3 RX3 Receive Data Output 3
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* PB7 RXCK RXCK Receive Clock Output
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* PB16 RXDV RXDV Receive Data Valid Output
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* PB17 RXER RXER Receive Error Output
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* PB20 TX0 TX0 Transmit Data Input 0
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* PB21 TX1 TX1 Transmit Data Input 1
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* PB12 TX2 TX2 Transmit Data Input 2
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* PB13 TX3 TX3 Transmit Data Input 3
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* PB14 TXCK TXCK Transmit Clock Input
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* PB15 TXEN TXEN Transmit Enable Input
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* PB6 TXER TXER Transmit Error Input
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* ---- ------------ ------- ----------------------------------
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*/
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#define PIO_EMAC0_COL PIO_EMAC0_COL_3
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#define PIO_EMAC0_CRS PIO_EMAC0_CRS_3
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#define PIO_EMAC0_MDC PIO_EMAC0_MDC_3
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#define PIO_EMAC0_MDIO PIO_EMAC0_MDIO_3
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#define PIO_EMAC0_RX0 PIO_EMAC0_RX0_3
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#define PIO_EMAC0_RX1 PIO_EMAC0_RX1_3
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#define PIO_EMAC0_RX2 PIO_EMAC0_RX2_3
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#define PIO_EMAC0_RX3 PIO_EMAC0_RX3_3
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#define PIO_EMAC0_RXCK PIO_EMAC0_RXCK_3
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#define PIO_EMAC0_RXDV PIO_EMAC0_RXDV_3
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#define PIO_EMAC0_RXER PIO_EMAC0_RXER_3
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#define PIO_EMAC0_TX0 PIO_EMAC0_TX0_3
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#define PIO_EMAC0_TX1 PIO_EMAC0_TX1_3
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#define PIO_EMAC0_TX2 PIO_EMAC0_TX2_3
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#define PIO_EMAC0_TX3 PIO_EMAC0_TX3_3
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#define PIO_EMAC0_TXCK PIO_EMAC0_TXCK_3
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#define PIO_EMAC0_TXEN PIO_EMAC0_TXEN_3
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#define PIO_EMAC0_TXER PIO_EMAC0_TXER_3
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/* Image Sensor Controller - ISC Pin Definitions ****************************/
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#define PIO_ISC_D0 PIO_ISC_D0_3
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#define PIO_ISC_D1 PIO_ISC_D1_3
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#define PIO_ISC_D2 PIO_ISC_D2_3
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#define PIO_ISC_D3 PIO_ISC_D3_3
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#define PIO_ISC_D4 PIO_ISC_D4_3
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#define PIO_ISC_D5 PIO_ISC_D5_3
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#define PIO_ISC_D6 PIO_ISC_D6_3
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#define PIO_ISC_D7 PIO_ISC_D7_3
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#define PIO_ISC_D8 PIO_ISC_D8_3
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#define PIO_ISC_D9 PIO_ISC_D9_3
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#define PIO_ISC_D10 PIO_ISC_D10_3
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#define PIO_ISC_D11 PIO_ISC_D11_3
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#define PIO_ISC_FIELD PIO_ISC_FIELD_3
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#define PIO_ISC_HSYNC PIO_ISC_HSYNC_3
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#define PIO_ISC_MCK PIO_ISC_MCK_3
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#define PIO_ISC_PCK PIO_ISC_PCK_3
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#define PIO_ISC_VSYNC PIO_ISC_VSYNC_3
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/* QSPI0 definitions ********************************************************/
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/* There is a QSPI Flash on board the SAMA5D2-XULT.
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* The QSPI Flash is connected to QSPI0 IOSET3 and can be used for
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* boot flash.
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*
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* ------------------------------ ------------------- ---------------------
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* SAMA5D2 PIO SIGNAL USAGE
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* ------------------------------ ------------------- ---------------------
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* PA23 QSPI0_CS QSPI Chip Selection
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* PA24 QSPI0_IO0 QSPI Data0
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* PA25 QSPI0_IO1 QSPI Data1
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* PA26 QSPI0_IO2 QSPI Data2
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* PA27 QSPI0_IO3 QSPI Data3
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* PA22 QSPI0_SCK QSPI Clock
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* ------------------------------ ------------------- ---------------------
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*/
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#define PIO_QSPI0_CS PIO_QSPI0_CS_3
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#define PIO_QSPI0_IO0 PIO_QSPI0_IO0_3
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#define PIO_QSPI0_IO1 PIO_QSPI0_IO1_3
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#define PIO_QSPI0_IO2 PIO_QSPI0_IO2_3
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#define PIO_QSPI0_IO3 PIO_QSPI0_IO3_3
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#define PIO_QSPI0_SCK PIO_QSPI0_SCK_3
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2019-08-15 18:19:17 +02:00
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/* LED definitions **********************************************************/
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/* There is an RGB LED on board the SAMA5D2-XULT.
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* The RED component is driven by the SDHC_CD pin (PA13) and so will not
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* be used. The LEDs are provided VDD_LED and so bringing the LED low will
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* will illuminated the LED.
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2015-09-05 20:13:12 +02:00
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*
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2019-08-15 18:19:17 +02:00
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* ------------------------------ ------------------- ---------------------
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2015-09-10 21:45:58 +02:00
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* SAMA5D2 PIO SIGNAL USAGE
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2019-08-15 18:19:17 +02:00
|
|
|
* ------------------------------ ------------------- ---------------------
|
2015-09-10 21:45:58 +02:00
|
|
|
* PA13 SDHC_CD_PA13 Red LED
|
|
|
|
* PB5 LED_GREEN_PB5 Green LED
|
|
|
|
* PB0 LED_BLUE_PB0 Blue LED
|
2019-08-15 18:19:17 +02:00
|
|
|
* ------------------------------ ------------------- ---------------------
|
2015-09-05 20:13:12 +02:00
|
|
|
*/
|
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|
|
|
#ifndef CONFIG_ARCH_LEDS
|
2019-08-15 18:19:17 +02:00
|
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|
2015-11-01 17:53:34 +01:00
|
|
|
/* LED index values for use with board_userled() */
|
2015-09-05 20:13:12 +02:00
|
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|
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|
|
#define BOARD_GREEN 0
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|
|
|
#define BOARD_BLUE 1
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|
|
|
#define BOARD_NLEDS 2
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|
|
|
2015-11-01 17:53:34 +01:00
|
|
|
/* LED bits for use with board_userled_all() */
|
2015-09-05 20:13:12 +02:00
|
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|
|
#define BOARD_GREEN_BIT (1 << BOARD_GREEN)
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|
|
#define BOARD_BLUE_BIT (1 << BOARD_BLUE)
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|
#else
|
2019-08-15 18:19:17 +02:00
|
|
|
|
2015-11-01 17:53:34 +01:00
|
|
|
/* LED index values for use with board_userled() */
|
2015-09-05 20:13:12 +02:00
|
|
|
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|
|
#define BOARD_BLUE 0
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|
|
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#define BOARD_NLEDS 1
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|
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|
2015-11-01 17:53:34 +01:00
|
|
|
/* LED bits for use with board_userled_all() */
|
2015-09-05 20:13:12 +02:00
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|
#define BOARD_BLUE_BIT (1 << BOARD_BLUE)
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|
#endif
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|
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
|
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* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
|
|
|
|
* events as follows. Note that only the GREEN LED is used in this case
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|
|
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*
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|
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|
* SYMBOL Val Meaning Green LED
|
2019-08-15 18:19:17 +02:00
|
|
|
* ----------------- --- ----------------------- -----------
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|
|
|
*/
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|
|
|
|
2015-09-05 20:13:12 +02:00
|
|
|
#define LED_STARTED 0 /* NuttX has been started OFF */
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|
|
|
#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
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|
|
|
#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
|
|
|
|
#define LED_STACKCREATED 1 /* Idle stack created ON */
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|
|
|
#define LED_INIRQ 2 /* In an interrupt N/C */
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|
|
|
#define LED_SIGNAL 2 /* In a signal handler N/C */
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|
|
|
#define LED_ASSERTION 2 /* An assertion failed N/C */
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|
|
|
#define LED_PANIC 3 /* The system has crashed Flash */
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|
|
|
#undef LED_IDLE /* MCU is is sleep mode Not used */
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|
|
|
2019-08-15 18:19:17 +02:00
|
|
|
/* Thus if the Green LED is statically on, NuttX has successfully booted
|
|
|
|
* and is, apparently, running normally.
|
|
|
|
* If LED is flashing at approximately 2Hz, then a fatal error has been
|
|
|
|
* detected and the system has halted.
|
2015-09-05 20:13:12 +02:00
|
|
|
*/
|
|
|
|
|
2019-08-15 18:19:17 +02:00
|
|
|
/* Button definitions *******************************************************/
|
|
|
|
|
2015-09-05 20:42:57 +02:00
|
|
|
/* A single button, PB_USER (PB6), is available on the SAMA5D2-XULT
|
2015-09-05 20:13:12 +02:00
|
|
|
*
|
2019-08-15 18:19:17 +02:00
|
|
|
* ------------------------------ ------------------- ----------------------
|
2015-09-05 20:42:57 +02:00
|
|
|
* SAMA5D2 PIO SIGNAL USAGE
|
2019-08-15 18:19:17 +02:00
|
|
|
* ------------------------------ ------------------- ----------------------
|
2015-09-05 20:42:57 +02:00
|
|
|
* PB6 USER_PB_PB6 PB_USER push button
|
2019-08-15 18:19:17 +02:00
|
|
|
* ------------------------------ ------------------- ----------------------
|
2015-09-05 20:13:12 +02:00
|
|
|
*
|
2019-08-15 18:19:17 +02:00
|
|
|
* Closing PB_USER will bring PB6 to ground so 1) PB6 should have a weak
|
|
|
|
* pull-up, and 2) when PB_USER is pressed, a low value will be senses.
|
2015-09-05 20:13:12 +02:00
|
|
|
*/
|
|
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|
|
|
|
#define BUTTON_USER 0
|
|
|
|
#define NUM_BUTTONS 1
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|
|
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|
|
|
|
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
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|
|
|
2019-08-15 18:19:17 +02:00
|
|
|
/* Pin disambiguation *******************************************************/
|
|
|
|
|
|
|
|
/* Alternative pin selections are provided with a numeric suffix like _1, _2,
|
|
|
|
* etc. Drivers, however, will use the pin selection without the numeric
|
|
|
|
* suffix.
|
|
|
|
* Additional definitions are required in this board.h file.
|
|
|
|
* For example, if we wanted the PCK0on PB26, then the following definition
|
|
|
|
* should appear in the board.h header file for that board:
|
2015-09-05 20:13:12 +02:00
|
|
|
*
|
|
|
|
* #define PIO_PMC_PCK0 PIO_PMC_PCK0_1
|
|
|
|
*
|
|
|
|
* The PCK logic will then automatically configure PB26 as the PCK0 pin.
|
|
|
|
*/
|
|
|
|
|
2015-09-13 23:46:31 +02:00
|
|
|
/* DEBUG / DBGU Port (J1). There is a TTL serial connection available on
|
|
|
|
* pins 2 and 3 of the DEBUG connector. This may be driven by UART1,
|
|
|
|
* depending upon the setting of JP2 (DBGU_PE on the schematic, DEBUG_DIS
|
|
|
|
* on the board):
|
|
|
|
*
|
|
|
|
* ---- ------------------------ -------------
|
|
|
|
* J1 SCHEMATIC SAMA5D2
|
|
|
|
* PIN NAME(s) PIO FUNCTION
|
|
|
|
* ---- ------------------------ -------------
|
|
|
|
* 2 DBGU_TXD DBGU_UTXD1_PD3 PD3 UTXD1
|
|
|
|
* 3 DBGU_RXD DBGU_URXD1_PD2 PD2 URXD1
|
|
|
|
* ---- ------------------------ -------------
|
2015-09-11 22:55:52 +02:00
|
|
|
*/
|
|
|
|
|
2019-02-11 21:55:18 +01:00
|
|
|
#define PIO_UART1_RXD PIO_UART1_RXD_1
|
|
|
|
#define PIO_UART1_TXD PIO_UART1_TXD_1
|
|
|
|
|
2019-12-31 15:10:46 +01:00
|
|
|
/* Standard UART on Arduino connector (J22) is UART2.
|
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* J22 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 7 URXD2 PD4 UART2 URXD2
|
|
|
|
* 8 UTXD2 PD5 UART2 UTXD2
|
|
|
|
* ---- ------- -------------
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PIO_UART2_RXD PIO_UART2_RXD_2
|
|
|
|
#define PIO_UART2_TXD PIO_UART2_TXD_2
|
|
|
|
|
|
|
|
/* Standard UART on Arduino connector (J17) is UART3.
|
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* J17 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 27 URXD3 PB11 UART3 URXD3
|
|
|
|
* 28 UTXD3 PB12 UART3 UTXD3
|
|
|
|
* ---- ------- -------------
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PIO_UART3_RXD PIO_UART3_RXD_1
|
|
|
|
#define PIO_UART3_TXD PIO_UART3_TXD_1
|
|
|
|
|
2015-09-11 22:55:52 +02:00
|
|
|
/* Standard UART on Arduino connector (J21) is FLEXCOM4.
|
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* J21 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 7 F4_TXD PD12 FLEXCOM4
|
|
|
|
* 8 F4_RXD PD13 FLEXCOM4
|
|
|
|
* ---- ------- -------------
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PIO_FLEXCOM4_IO0 PIO_FLEXCOM4_IO0_2
|
|
|
|
#define PIO_FLEXCOM4_IO1 PIO_FLEXCOM4_IO1_2
|
2022-05-28 06:14:42 +02:00
|
|
|
#define PIO_FLEXCOM4_IO2 PIO_FLEXCOM4_IO1_2
|
|
|
|
#define PIO_FLEXCOM4_IO3 PIO_FLEXCOM4_IO3_2
|
|
|
|
#define PIO_FLEXCOM4_IO4 PIO_FLEXCOM4_IO4_2
|
|
|
|
|
|
|
|
/* PWM channel 0 */
|
|
|
|
|
|
|
|
#define PIO_PWM0_H PIO_PWM0_H0
|
2015-09-11 22:55:52 +02:00
|
|
|
|
|
|
|
/* Other USARTs are available on J22:
|
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* J22 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 3 F0_TXD PB28 FLEXCOM0
|
|
|
|
* 4 F0_RXD PB29 FLEXCOM0
|
|
|
|
* 5 F3_TXD PB23 FLEXCOM3
|
|
|
|
* 6 F3_RXD PB22 FLEXCOM3
|
|
|
|
* ---- ------- -------------
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PIO_FLEXCOM3_IO0 PIO_FLEXCOM3_IO0_2
|
|
|
|
#define PIO_FLEXCOM3_IO1 PIO_FLEXCOM3_IO1_2
|
2022-05-28 06:14:42 +02:00
|
|
|
#define PIO_FLEXCOM3_IO2 PIO_FLEXCOM3_IO1_2
|
|
|
|
#define PIO_FLEXCOM3_IO3 PIO_FLEXCOM3_IO3_2
|
|
|
|
#define PIO_FLEXCOM3_IO4 PIO_FLEXCOM3_IO4_2
|
|
|
|
|
|
|
|
#define PIO_FLEXCOM2_IO0 PIO_FLEXCOM2_IO0_2
|
|
|
|
#define PIO_FLEXCOM2_IO1 PIO_FLEXCOM2_IO1_2
|
|
|
|
#define PIO_FLEXCOM2_IO3 PIO_FLEXCOM2_IO3_2
|
|
|
|
#define PIO_FLEXCOM2_IO4 PIO_FLEXCOM2_IO4_2
|
2015-09-11 22:55:52 +02:00
|
|
|
|
2019-02-11 21:55:18 +01:00
|
|
|
/* UARTs available on EXT1
|
2015-09-11 22:55:52 +02:00
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* EXT1 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 13 UART_RX PA23 FLEXCOM1
|
|
|
|
* 14 UART_TX PA24 FLEXCOM1
|
|
|
|
* ---- ------- ---- --------
|
|
|
|
*/
|
|
|
|
|
2019-02-11 21:55:18 +01:00
|
|
|
/* UARTs available on EXT2
|
2015-09-11 22:55:52 +02:00
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* EXT2 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 13 UART_RX PB29 FLEXCOM0
|
|
|
|
* 14 UART_TX PB28 FLEXCOM0
|
|
|
|
* ---- ------- ---- --------
|
|
|
|
*/
|
|
|
|
|
2022-05-28 06:14:42 +02:00
|
|
|
/* SPIs available on EXT1
|
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* EXT1 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 15 SPI_SS PD29 SPI1
|
|
|
|
* 16 SPI_MOSI PD26 SPI1
|
|
|
|
* 17 SPI_MISO PD27 SPI1
|
|
|
|
* 18 SPI_SCK PD25 SPI1
|
|
|
|
* ---- ------- ---- --------
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PIO_SPI1_MISO PIO_SPI1_MISO_1
|
|
|
|
#define PIO_SPI1_MOSI PIO_SPI1_MOSI_1
|
|
|
|
#define PIO_SPI1_NPCS1 PIO_SPI1_NPCS1_1
|
|
|
|
#define PIO_SPI1_SPCK PIO_SPI1_SPCK_1
|
|
|
|
|
|
|
|
/* SPI0 Definition on EXP */
|
|
|
|
|
|
|
|
#define PIO_SPI0_MISO PIO_SPI0_MISO_1
|
|
|
|
#define PIO_SPI0_MOSI PIO_SPI0_MOSI_1
|
|
|
|
#define PIO_SPI0_NPCS0 PIO_SPI0_NPCS0_1
|
|
|
|
#define PIO_SPI0_SPCK PIO_SPI0_SPCK_1
|
|
|
|
|
|
|
|
/* CANs are available on J9:
|
|
|
|
*
|
|
|
|
* ---- ------- -------------
|
|
|
|
* J9 BOARD SAMA5D2
|
|
|
|
* PIN NAME PIO FUNCTION
|
|
|
|
* ---- ------- -------------
|
|
|
|
* 5 CANRX1 PC27 MCAN1-RX
|
|
|
|
* 6 CANTX1 PC26 MCAN1-TX
|
|
|
|
* 7 CANRX0 PC11 MCAN0-RX
|
|
|
|
* 8 CANTX0 PC10 MCAN0-TX
|
|
|
|
* ---- ------- -------------
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PIO_MCAN0_RX PIO_MCAN0_RX_2
|
|
|
|
#define PIO_MCAN0_TX PIO_MCAN0_TX_2
|
|
|
|
|
2020-07-16 19:31:53 +02:00
|
|
|
/* SDIO - Used for both Port 0 & 1 ******************************************/
|
|
|
|
|
|
|
|
/* 386 KHz for initial inquiry stuff */
|
|
|
|
|
|
|
|
#define BOARD_SDMMC_IDMODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV256
|
|
|
|
#define BOARD_SDMMC_IDMODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(2)
|
|
|
|
|
|
|
|
/* 24.8MHz for other modes */
|
|
|
|
|
|
|
|
#define BOARD_SDMMC_MMCMODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
|
|
|
|
#define BOARD_SDMMC_MMCMODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
|
|
|
|
|
|
|
|
#define BOARD_SDMMC_SD1MODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
|
|
|
|
#define BOARD_SDMMC_SD1MODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
|
|
|
|
|
|
|
|
#define BOARD_SDMMC_SD4MODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
|
|
|
|
#define BOARD_SDMMC_SD4MODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
|
|
|
|
|
2019-08-15 18:19:17 +02:00
|
|
|
/****************************************************************************
|
2015-09-05 20:13:12 +02:00
|
|
|
* Assembly Language Macros
|
2019-08-15 18:19:17 +02:00
|
|
|
****************************************************************************/
|
2015-09-05 20:13:12 +02:00
|
|
|
|
|
|
|
#ifdef __ASSEMBLY__
|
2019-08-15 18:19:17 +02:00
|
|
|
.macro config_sdram
|
|
|
|
.endm
|
2015-09-05 20:13:12 +02:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
2020-01-31 19:07:39 +01:00
|
|
|
#endif /* __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_H */
|