2015-03-05 17:00:24 +01:00
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/************************************************************************************
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* arch/arm/include/samv7/chip.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_SAMV7_CHIP_H
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#define __ARCH_ARM_INCLUDE_SAMV7_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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2015-11-14 18:36:21 +01:00
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/* SAME70Q19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAME70Q20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAME70Q21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP144 and LFBGA144 packaging
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*/
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#if defined(CONFIG_ARCH_CHIP_SAME70Q19) || defined(CONFIG_ARCH_CHIP_SAME70Q20) || \
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defined(CONFIG_ARCH_CHIP_SAME70Q21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAME70Q19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAME70Q20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAME70Q21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 1 /* Have External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 1 /* Have SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 0 /* No MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 24 /* 24 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 36 /* 36 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
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# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
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# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 0 /* No USB full speed device */
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# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAME70N19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAME70N20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAME70N21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP100 and TFBGA100 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAME70N19) || defined(CONFIG_ARCH_CHIP_SAME70N20) || \
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defined(CONFIG_ARCH_CHIP_SAME70N21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAME70N19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAME70N20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAME70N21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 0 /* No MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 10 /* 10 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 9 /* 9 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 1 /* 1 SPI, SPI0 only */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
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# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
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# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 0 /* No USB full speed device */
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# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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/* SAME70J19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAME70J20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAME70J21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP64 and TFBGA64 packaging
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*/
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#elif defined(CONFIG_ARCH_CHIP_SAME70J19) || defined(CONFIG_ARCH_CHIP_SAME70J20) || \
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defined(CONFIG_ARCH_CHIP_SAME70J21)
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAME70J19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAME70J20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAME70J21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#endif
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 0 /* No MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 5 /* 5 12-bit ADC channels */
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# define SAMV7_NDAC12 1 /* 1 12-bit DAC channel */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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# define SAMV7_NTCCHIO 3 /* 3 Timer/counter channels I/O */
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# define SAMV7_NUSART 0 /* No USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 0 /* No Quad SPI */
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# define SAMV7_NSPI 1 /* No SPI, QSPI functions in SPI mode only */
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# define SAMV7_NTWIHS 2 /* 2 TWIHS */
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# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
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# define SAMV7_NCAN 1 /* 1 CAN port */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 0 /* No Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 0 /* No 12-bit ISI interface */
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# define SAMV7_NISI8 1 /* 1 8-bit ISI interface */
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# define SAMV7_NSSC 1 /* 1 SSC */
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# define SAMV7_NUDPHS 0 /* No USB high speed device */
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# define SAMV7_NUHPHS 0 /* No USB high speed embedded Mini-Host */
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# define SAMV7_NUDPFS 1 /* 1 USB full speed device */
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# define SAMV7_NUHPFS 1 /* 1 USB full speed embedded host */
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# define SAMV7_NACC 1 /* 1 Analog comparator */
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# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
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2015-03-05 17:00:24 +01:00
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/* SAMV71Q19 - 512 Kbytes FLASH / 256 Kbytes SRAM
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* SAMV71Q20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
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* SAMV71Q21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
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*
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* LQFP144 and LFBGA144 packaging
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*/
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2015-11-14 18:36:21 +01:00
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#elif defined(CONFIG_ARCH_CHIP_SAMV71Q19) || defined(CONFIG_ARCH_CHIP_SAMV71Q20) || \
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defined(CONFIG_ARCH_CHIP_SAMV71Q21)
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2015-03-05 17:00:24 +01:00
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/* Internal memory */
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#if defined(CONFIG_ARCH_CHIP_SAMV71Q19)
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# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
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# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
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#elif defined(CONFIG_ARCH_CHIP_SAMV71Q20)
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# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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#else /* if defined(CONFIG_ARCH_CHIP_SAMV71Q21) */
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# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
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2015-03-07 18:46:54 +01:00
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# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
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2015-03-05 17:00:24 +01:00
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#endif
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2015-11-14 18:36:21 +01:00
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# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
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2015-03-05 17:00:24 +01:00
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/* Peripherals */
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# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
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# define SAMV7_NEBI 1 /* Have External Bus Interface (EBI) */
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# define SAMV7_NSDRAMC 1 /* Have SDRAM controller (SDRAMC) */
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# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
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# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
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# define SAMV7_NADC12 24 /* 24 12-bit ADC channels */
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# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
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# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
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2015-11-14 18:36:21 +01:00
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# define SAMV7_NTCCHIO 36 /* 36 Timer/counter channels I/O */
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2015-03-05 17:00:24 +01:00
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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2015-08-14 21:11:40 +02:00
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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2015-03-05 17:00:24 +01:00
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# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
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2015-03-12 17:58:11 +01:00
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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2015-03-05 17:00:24 +01:00
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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# define SAMV7_NCAN 2 /* 2 CAN ports */
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# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
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# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
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# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
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# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
|
|
|
|
|
# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
|
|
|
|
|
# define SAMV7_NSSC 1 /* 1 SSC */
|
|
|
|
|
# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
|
|
|
|
|
# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
|
|
|
|
|
# define SAMV7_NUDPFS 0 /* No USB full speed device */
|
|
|
|
|
# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
|
2015-03-05 20:51:39 +01:00
|
|
|
# define SAMV7_NACC 1 /* 1 Analog comparator */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
|
|
|
|
|
|
|
|
|
|
/* SAMV71N19 - 512 Kbytes FLASH / 256 Kbytes SRAM
|
|
|
|
|
* SAMV71N20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
|
|
|
|
|
* SAMV71N21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
|
|
|
|
|
*
|
|
|
|
|
* LQFP100 and TFBGA100 packaging
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMV71N19) || defined(CONFIG_ARCH_CHIP_SAMV71N20) || \
|
|
|
|
|
defined(CONFIG_ARCH_CHIP_SAMV71N21)
|
|
|
|
|
|
|
|
|
|
/* Internal memory */
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ARCH_CHIP_SAMV71N19)
|
|
|
|
|
# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
|
|
|
|
|
# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
|
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMV71N20)
|
|
|
|
|
# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
|
|
|
|
|
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
|
|
|
|
|
#else /* if defined(CONFIG_ARCH_CHIP_SAMV71N21) */
|
|
|
|
|
# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
|
2015-03-07 18:46:54 +01:00
|
|
|
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
|
2015-03-05 17:00:24 +01:00
|
|
|
#endif
|
|
|
|
|
|
2015-11-14 18:36:21 +01:00
|
|
|
# define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
|
2015-03-05 17:00:24 +01:00
|
|
|
|
|
|
|
|
/* Peripherals */
|
|
|
|
|
|
|
|
|
|
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
|
|
|
|
|
# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
|
|
|
|
|
# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
|
|
|
|
|
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
|
|
|
|
|
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
|
|
|
|
|
# define SAMV7_NADC12 10 /* 10 12-bit ADC channels */
|
|
|
|
|
# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
|
|
|
|
|
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
|
2015-11-14 18:36:21 +01:00
|
|
|
# define SAMV7_NTCCHIO 9 /* 9 Timer/counter channels I/O */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NUSART 3 /* 3 USARTs */
|
|
|
|
|
# define SAMV7_NUART 5 /* 5 UARTs */
|
2015-08-14 21:11:40 +02:00
|
|
|
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
|
2015-03-12 17:58:11 +01:00
|
|
|
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
|
|
|
|
|
# define SAMV7_NCAN 2 /* 2 CAN ports */
|
|
|
|
|
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
|
|
|
|
|
# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
|
|
|
|
|
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
|
|
|
|
|
# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
|
|
|
|
|
# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
|
|
|
|
|
# define SAMV7_NSSC 1 /* 1 SSC */
|
|
|
|
|
# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
|
|
|
|
|
# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
|
|
|
|
|
# define SAMV7_NUDPFS 0 /* No USB full speed device */
|
|
|
|
|
# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
|
2015-03-05 20:51:39 +01:00
|
|
|
# define SAMV7_NACC 1 /* 1 Analog comparator */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
|
|
|
|
|
|
|
|
|
|
/* SAMV71J19 - 512 Kbytes FLASH / 256 Kbytes SRAM
|
|
|
|
|
* SAMV71J20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
|
|
|
|
|
* SAMV71J21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
|
|
|
|
|
*
|
|
|
|
|
* LQFP64, TFBGA64, and QFN64 packaging
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMV71J19) || defined(CONFIG_ARCH_CHIP_SAMV71J20) || \
|
|
|
|
|
defined(CONFIG_ARCH_CHIP_SAMV71J21)
|
|
|
|
|
|
|
|
|
|
/* Internal memory */
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ARCH_CHIP_SAMV71J19)
|
|
|
|
|
# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
|
|
|
|
|
# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
|
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMV71J20)
|
|
|
|
|
# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
|
|
|
|
|
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
|
|
|
|
|
#else /* if defined(CONFIG_ARCH_CHIP_SAMV71J21) */
|
|
|
|
|
# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
|
2015-03-07 18:46:54 +01:00
|
|
|
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
|
2015-03-05 17:00:24 +01:00
|
|
|
#endif
|
|
|
|
|
|
2015-11-14 18:36:21 +01:00
|
|
|
#define SAMV7_BSRAM_SIZE (1*1024) /* 1KB Backup SRAM */
|
2015-03-05 17:00:24 +01:00
|
|
|
|
|
|
|
|
/* Peripherals */
|
|
|
|
|
|
|
|
|
|
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
|
|
|
|
|
# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
|
|
|
|
|
# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
|
|
|
|
|
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
|
|
|
|
|
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
|
|
|
|
|
# define SAMV7_NADC12 5 /* 5 12-bit ADC channels */
|
|
|
|
|
# define SAMV7_NDAC12 1 /* 1 12-bit DAC channels */
|
|
|
|
|
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
|
2015-11-14 18:36:21 +01:00
|
|
|
# define SAMV7_NTCCHIO 3 /* 3 Timer/counter channels I/O */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NUSART 0 /* No USARTs */
|
|
|
|
|
# define SAMV7_NUART 5 /* 5 UARTs */
|
|
|
|
|
# define SAMV7_NQSPI 0 /* No Quad SPI */
|
|
|
|
|
# define SAMV7_NSPI 1 /* 1 SPI, QSPI functions in SPI mode only */
|
2015-03-12 17:58:11 +01:00
|
|
|
# define SAMV7_NTWIHS 2 /* 2 TWIHS */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
|
|
|
|
|
# define SAMV7_NCAN 1 /* 1 CAN port */
|
|
|
|
|
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
|
|
|
|
|
# define SAMV7_NEMACMII 0 /* No Ethernet MAC MII interface */
|
|
|
|
|
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
|
|
|
|
|
# define SAMV7_NISI12 0 /* No 12-bit ISI interface */
|
|
|
|
|
# define SAMV7_NISI8 1 /* 1 8-bit ISI interface */
|
|
|
|
|
# define SAMV7_NSSC 1 /* 1 SSC */
|
|
|
|
|
# define SAMV7_NUDPHS 0 /* No USB high speed device */
|
|
|
|
|
# define SAMV7_NUHPHS 0 /* No USB high speed embedded Mini-Host */
|
|
|
|
|
# define SAMV7_NUDPFS 1 /* 1 USB full speed device */
|
|
|
|
|
# define SAMV7_NUHPFS 1 /* 1 USB full speed embedded host */
|
2015-03-05 20:51:39 +01:00
|
|
|
# define SAMV7_NACC 1 /* 1 Analog comparator */
|
2015-03-05 17:00:24 +01:00
|
|
|
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
# error "Unknown SAMV7 chip type"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* NVIC priority levels *************************************************************/
|
|
|
|
|
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
|
|
|
|
|
* the priority of the corresponding interrupt. The processor implements only
|
2016-01-25 14:36:26 +01:00
|
|
|
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
|
2015-03-05 17:00:24 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
|
|
|
|
|
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
|
|
|
|
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
|
|
|
|
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
|
|
|
|
|
|
|
|
|
|
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
|
|
|
|
|
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
|
|
|
|
|
* interrupts will not have execution priority. SVCall must have execution
|
|
|
|
|
* priority in all cases.
|
|
|
|
|
*
|
|
|
|
|
* In the normal cases, interrupts are not nest-able and all interrupts run
|
|
|
|
|
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
|
|
|
|
|
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
|
|
|
|
|
*
|
|
|
|
|
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
|
|
|
|
|
* high priority interrupts are supported. These are not "nested" in the
|
|
|
|
|
* normal sense of the word. These high priority interrupts can interrupt
|
|
|
|
|
* normal processing but execute outside of OS (although they can "get back
|
|
|
|
|
* into the game" via a PendSV interrupt).
|
|
|
|
|
*
|
|
|
|
|
* In the normal course of things, interrupts must occasionally be disabled
|
2016-02-14 23:11:25 +01:00
|
|
|
* using the up_irq_save() inline function to prevent contention in use of
|
2015-03-05 17:00:24 +01:00
|
|
|
* resources that may be shared between interrupt level and non-interrupt
|
|
|
|
|
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
|
|
|
|
|
* do we disable all interrupts (except SVCall), or do we only disable the
|
|
|
|
|
* "normal" interrupts. Since the high priority interrupts cannot interact
|
|
|
|
|
* with the OS, you may want to permit the high priority interrupts even if
|
|
|
|
|
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
|
|
|
|
|
* used to select either behavior:
|
|
|
|
|
*
|
|
|
|
|
* ----------------------------+--------------+----------------------------
|
|
|
|
|
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
|
|
|
|
|
* ----------------------------+--------------+--------------+-------------
|
|
|
|
|
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
|
|
|
|
|
* ----------------------------+--------------+--------------+-------------
|
|
|
|
|
* | | | SVCall
|
|
|
|
|
* | SVCall | SVCall | HIGH
|
|
|
|
|
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
|
|
|
|
|
* | | MAXNORMAL |
|
|
|
|
|
* ----------------------------+--------------+--------------+-------------
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
|
|
|
|
|
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
|
|
|
|
|
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
|
|
|
|
|
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
|
|
|
|
|
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
|
|
|
|
|
#else
|
|
|
|
|
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
|
|
|
|
|
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
|
|
|
|
|
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
|
|
|
|
|
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Public Types
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Public Data
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Public Functions
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_SAMV7_CHIP_H */
|
