2021-05-20 22:07:54 +02:00
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/****************************************************************************
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* arch/xtensa/include/esp32s2/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H
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#define __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/esp32s2/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2022-03-07 20:15:32 +01:00
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#define ESP32S2_INT_PRIO_DEF 1
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2021-05-20 22:07:54 +02:00
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/* Interrupt Matrix
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*
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2022-03-07 20:15:32 +01:00
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* The Interrupt Matrix embedded in the ESP32-S2 independently allocates
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* peripheral interrupt sources to the CPU peripheral interrupts, so as to
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* timely inform the CPU to process the interrupts once the interrupt signals
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* are generated.
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* Peripheral interrupt sources must be routed to CPU peripheral
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* interrupts via this interrupt matrix due to the following considerations:
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* - ESP32-S2 has 95 peripheral interrupt sources. To map them to 32 CPU
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* interrupts, this matrix is needed.
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* - Through this matrix, one peripheral interrupt source can be mapped to
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* multiple CPU interrupts according to application requirements.
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*
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* Features:
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* - Accept 95 peripheral interrupt sources as input.
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* - Generate 26 peripheral interrupts to the CPU output. Note that the
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* remaining 6 CPU interrupts are internal interrupts.
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* - Support disabling CPU non-maskable interrupt (NMI) sources.
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* - Support querying current interrupt status of peripheral interrupt
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* sources.
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2021-05-20 22:07:54 +02:00
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*/
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2022-03-07 20:15:32 +01:00
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/* RESERVED interrupts: 0, 1, 3, 4, 5, 6, 7, 8, 9 */
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#define ESP32S2_PERIPH_PWR 2
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/* RESERVED interrupts: 10, 11, 12, 14 */
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#define ESP32S2_PERIPH_UHCI0 13
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#define ESP32S2_PERIPH_TG_T0_LEVEL 15
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#define ESP32S2_PERIPH_TG_T1_LEVEL 16
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#define ESP32S2_PERIPH_TG_WDT_LEVEL 17
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#define ESP32S2_PERIPH_TG_LACT_LEVEL 18
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#define ESP32S2_PERIPH_TG1_T0_LEVEL 19
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/* RESERVED interrupts: 25, 26 */
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#define ESP32S2_PERIPH_TG1_T1_LEVEL 20
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#define ESP32S2_PERIPH_TG1_WDT_LEVEL 21
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#define ESP32S2_PERIPH_TG1_LACT_LEVEL 22
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#define ESP32S2_PERIPH_GPIO_INT_PRO 23
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#define ESP32S2_PERIPH_GPIO_INT_PRO_NMI 24
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#define ESP32S2_PERIPH_DEDICATED_GPIO_IN 27
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#define ESP32S2_PERIPH_INT_FROM_CPU0 28
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#define ESP32S2_PERIPH_INT_FROM_CPU1 29
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/* RESERVED interrupts: 39 */
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#define ESP32S2_PERIPH_INT_FROM_CPU2 30
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#define ESP32S2_PERIPH_INT_FROM_CPU3 31
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#define ESP32S2_PERIPH_SPI1 32
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#define ESP32S2_PERIPH_SPI2 33
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#define ESP32S2_PERIPH_SPI3 34
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#define ESP32S2_PERIPH_I2S0 35
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#define ESP32S2_PERIPH_UART 37
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#define ESP32S2_PERIPH_UART1 38
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/* RESERVED interrupts: 40, 41, 42, 43, 44 */
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#define ESP32S2_PERIPH_LEDC 45
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#define ESP32S2_PERIPH_EFUSE 46
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#define ESP32S2_PERIPH_CAN 47
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#define ESP32S2_PERIPH_USB 48
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#define ESP32S2_PERIPH_RTC_CORE 49
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/* RESERVED interrupts: 59 */
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#define ESP32S2_PERIPH_RMT 50
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#define ESP32S2_PERIPH_PCNT 51
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#define ESP32S2_PERIPH_I2C_EXT0 52
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#define ESP32S2_PERIPH_I2C_EXT1 53
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#define ESP32S2_PERIPH_RSA 54
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#define ESP32S2_PERIPH_SHA 55
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#define ESP32S2_PERIPH_AES 56
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#define ESP32S2_PERIPH_SPI2_DMA 57
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#define ESP32S2_PERIPH_SPI3_DMA 58
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#define ESP32S2_PERIPH_TIMER 60
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#define ESP32S2_PERIPH_TIMER_INT2 61
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#define ESP32S2_PERIPH_TG_T0_EDGE 62
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#define ESP32S2_PERIPH_TG_T1_EDGE 63
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#define ESP32S2_PERIPH_TG_WDT_EDGE 64
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#define ESP32S2_PERIPH_TG_LACT_EDGE 65
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#define ESP32S2_PERIPH_TG1_T0_EDGE 66
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#define ESP32S2_PERIPH_TG1_T1_EDGE 67
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#define ESP32S2_PERIPH_TG1_WDT_EDGE 68
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#define ESP32S2_PERIPH_TG1_LACT_EDGE 69
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#define ESP32S2_PERIPH_CACHE_IA 70
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#define ESP32S2_PERIPH_SYSTIMER_TARGET0 71
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#define ESP32S2_PERIPH_SYSTIMER_TARGET1 72
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#define ESP32S2_PERIPH_SYSTIMER_TARGET2 73
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#define ESP32S2_PERIPH_ASSIST_DEBUG 74
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#define ESP32S2_PERIPH_PMS_PRO_IRAM0_ILG 75
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#define ESP32S2_PERIPH_PMS_PRO_DRAM0_ILG 76
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#define ESP32S2_PERIPH_PMS_PRO_DPORT_ILG 77
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#define ESP32S2_PERIPH_PMS_PRO_AHB_ILG 78
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#define ESP32S2_PERIPH_PMS_PRO_CACHE_ILG 79
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/* RESERVED interrupts: 85, 86 */
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#define ESP32S2_PERIPH_PMS_DMA_APB_I_ILG 80
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#define ESP32S2_PERIPH_PMS_DMA_RX_I_ILG 81
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#define ESP32S2_PERIPH_PMS_DMA_TX_I_ILG 82
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#define ESP32S2_PERIPH_SPI_MEM_REJECT 83
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#define ESP32S2_PERIPH_DMA_COPY 84
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#define ESP32S2_PERIPH_DCACHE_PRELOAD 87
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#define ESP32S2_PERIPH_ICACHE_PRELOAD 88
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#define ESP32S2_PERIPH_APB_ADC 89
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#define ESP32S2_PERIPH_CRYPTO_DMA 90
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#define ESP32S2_PERIPH_CPU_PERI_ERR 91
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#define ESP32S2_PERIPH_APB_PERI_ERR 92
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#define ESP32S2_PERIPH_DCACHE_SYNC 93
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#define ESP32S2_PERIPH_ICACHE_SYNC 94
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/* Total number of peripherals */
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2022-03-07 20:15:32 +01:00
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#define ESP32S2_NPERIPHERALS 95
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/* Exceptions
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*
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* IRAM Offset Description
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* 0x0000 Windows
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* 0x0180 Level 2 interrupt
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* 0x01c0 Level 3 interrupt
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* 0x0200 Level 4 interrupt
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* 0x0240 Level 5 interrupt
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* 0x0280 Debug exception
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* 0x02c0 NMI exception
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* 0x0300 Kernel exception
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* 0x0340 User exception
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* 0x03c0 Double exception
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*
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* REVISIT: In more architectures supported by NuttX, exception errors
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* tie into the normal interrupt handling via special IRQ numbers.
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* It is still to be determined what will be done for the ESP32S2.
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*
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*/
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/* IRQ numbers for internal interrupts that are dispatched like peripheral
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* interrupts
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*/
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#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
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#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
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#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
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#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
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#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
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2022-02-18 07:16:48 +01:00
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#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
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#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
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/* IRQ numbers for peripheral interrupts coming through the Interrupt
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* Matrix.
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*/
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2022-03-07 20:15:32 +01:00
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#define ESP32S2_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
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#define ESP32S2_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
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#define ESP32S2_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PWR)
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#define ESP32S2_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_UHCI0)
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#define ESP32S2_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_T0_LEVEL)
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#define ESP32S2_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_T1_LEVEL)
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#define ESP32S2_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_WDT_LEVEL)
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#define ESP32S2_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_LACT_LEVEL)
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#define ESP32S2_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_T0_LEVEL)
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#define ESP32S2_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_T1_LEVEL)
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#define ESP32S2_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_WDT_LEVEL)
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#define ESP32S2_IRQ_TG1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_LACT_LEVEL)
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#define ESP32S2_IRQ_GPIO_INT_PRO (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_GPIO_INT_PRO)
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#define ESP32S2_IRQ_GPIO_INT_PRO_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_GPIO_INT_PRO_NMI)
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#define ESP32S2_IRQ_DEDICATED_GPIO_IN (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_DEDICATED_GPIO_IN)
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#define ESP32S2_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_INT_FROM_CPU0)
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#define ESP32S2_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_INT_FROM_CPU1)
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#define ESP32S2_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_INT_FROM_CPU2)
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#define ESP32S2_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_INT_FROM_CPU3)
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#define ESP32S2_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SPI1)
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#define ESP32S2_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SPI2)
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#define ESP32S2_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SPI3)
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#define ESP32S2_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_I2S0)
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#define ESP32S2_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_I2S1)
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#define ESP32S2_IRQ_UART (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_UART)
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#define ESP32S2_IRQ_UART1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_UART1)
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#define ESP32S2_IRQ_LEDC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_LEDC)
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#define ESP32S2_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_EFUSE)
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#define ESP32S2_IRQ_CAN (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_CAN)
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#define ESP32S2_IRQ_USB (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_USB)
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#define ESP32S2_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_RTC_CORE)
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#define ESP32S2_IRQ_RMT (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_RMT)
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#define ESP32S2_IRQ_PCNT (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PCNT)
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#define ESP32S2_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_I2C_EXT0)
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#define ESP32S2_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_I2C_EXT1)
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#define ESP32S2_IRQ_RSA (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_RSA)
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#define ESP32S2_IRQ_SHA (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SHA)
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#define ESP32S2_IRQ_AES (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_AES)
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#define ESP32S2_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SPI2_DMA)
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#define ESP32S2_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SPI3_DMA)
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#define ESP32S2_IRQ_TIMER (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TIMER)
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#define ESP32S2_IRQ_TIMER_INT2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TIMER_INT2)
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#define ESP32S2_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_T0_EDGE)
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#define ESP32S2_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_T1_EDGE)
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#define ESP32S2_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_WDT_EDGE)
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#define ESP32S2_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG_LACT_EDGE)
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#define ESP32S2_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_T0_EDGE)
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#define ESP32S2_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_T1_EDGE)
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#define ESP32S2_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_WDT_EDGE)
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#define ESP32S2_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_TG1_LACT_EDGE)
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#define ESP32S2_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_CACHE_IA)
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#define ESP32S2_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SYSTIMER_TARGET0)
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#define ESP32S2_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SYSTIMER_TARGET1)
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#define ESP32S2_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SYSTIMER_TARGET2)
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#define ESP32S2_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_ASSIST_DEBUG)
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#define ESP32S2_IRQ_PMS_PRO_IRAM0_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_PRO_IRAM0_ILG)
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#define ESP32S2_IRQ_PMS_PRO_DRAM0_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_PRO_DRAM0_ILG)
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#define ESP32S2_IRQ_PMS_PRO_DPORT_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_PRO_DPORT_ILG)
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#define ESP32S2_IRQ_PMS_PRO_AHB_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_PRO_AHB_ILG)
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#define ESP32S2_IRQ_PMS_PRO_CACHE_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_PRO_CACHE_ILG)
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#define ESP32S2_IRQ_PMS_DMA_APB_I_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_DMA_APB_I_ILG)
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#define ESP32S2_IRQ_PMS_DMA_RX_I_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_DMA_RX_I_ILG)
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#define ESP32S2_IRQ_PMS_DMA_TX_I_ILG (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_PMS_DMA_TX_I_ILG)
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#define ESP32S2_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_SPI_MEM_REJECT)
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#define ESP32S2_IRQ_DMA_COPY (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_DMA_COPY)
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#define ESP32S2_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_DCACHE_PRELOAD)
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#define ESP32S2_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_ICACHE_PRELOAD)
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#define ESP32S2_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_APB_ADC)
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#define ESP32S2_IRQ_CRYPTO_DMA (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_CRYPTO_DMA)
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#define ESP32S2_IRQ_CPU_PERI_ERR (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_CPU_PERI_ERR)
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#define ESP32S2_IRQ_APB_PERI_ERE (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_APB_PERI_ERR)
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#define ESP32S2_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_DCACHE_SYNC)
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#define ESP32S2_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_ICACHE_SYNC)
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2021-05-20 22:07:54 +02:00
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#define ESP32S2_NIRQ_PERIPH ESP32S2_NPERIPHERALS
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2022-03-07 20:15:32 +01:00
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/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
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* as a second level of decoding: The first level dispatches to the GPIO
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* interrupt handler. The second to the decoded GPIO interrupt handler.
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2021-05-20 22:07:54 +02:00
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*/
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#ifdef CONFIG_ESP32S2_GPIO_IRQ
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# define ESP32S2_NIRQ_GPIO 40
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2022-03-07 20:15:32 +01:00
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# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH)
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# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ + ESP32S2_NIRQ_GPIO - 1)
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2021-05-20 22:07:54 +02:00
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# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
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# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
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#else
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# define ESP32S2_NIRQ_GPIO 0
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#endif
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/* Total number of interrupts */
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2022-03-07 20:15:32 +01:00
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#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO)
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2021-05-20 22:07:54 +02:00
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/* Xtensa CPU Interrupts.
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*
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2022-03-07 20:15:32 +01:00
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* The CPU has 32 interrupts, of which 26 can be mapped to peripheral
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* interrupts:
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2021-05-20 22:07:54 +02:00
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*
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* Level triggered peripherals (21 total):
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* 0-5, 8-9, 12-13, 17-18 - Priority 1
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* 19-21 - Priority 2
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* 23, 27 - Priority 3
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* 24-25 - Priority 4
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* 26, 31 - Priority 5
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* Edge triggered peripherals (4 total):
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* 10 - Priority 1
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* 22 - Priority 3
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* 28, 30 - Priority 4
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* NMI (1 total):
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* 14 - NMI
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*
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* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
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2022-03-07 20:15:32 +01:00
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* INTERRUPT_PRO_*_MAP_REG. There are a pair of these registers for each
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* peripheral source. Multiple peripheral interrupt sources can be mapped to
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* the same CPU interrupt.
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2021-05-20 22:07:54 +02:00
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*
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* The remaining, six, internal CPU interrupts are:
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*
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* 6 Timer0 - Priority 1
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* 7 Software - Priority 1
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* 11 Profiling - Priority 3
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* 15 Timer1 - Priority 3
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* 16 Timer2 - Priority 5
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* 29 Software - Priority 3
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*
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2022-03-07 20:15:32 +01:00
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* A peripheral interrupt can be disabled.
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2021-05-20 22:07:54 +02:00
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*/
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#define ESP32S2_CPUINT_LEVELPERIPH_0 0
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#define ESP32S2_CPUINT_LEVELPERIPH_1 1
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#define ESP32S2_CPUINT_LEVELPERIPH_2 2
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#define ESP32S2_CPUINT_LEVELPERIPH_3 3
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#define ESP32S2_CPUINT_LEVELPERIPH_4 4
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#define ESP32S2_CPUINT_LEVELPERIPH_5 5
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#define ESP32S2_CPUINT_LEVELPERIPH_6 8
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#define ESP32S2_CPUINT_LEVELPERIPH_7 9
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#define ESP32S2_CPUINT_LEVELPERIPH_8 12
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#define ESP32S2_CPUINT_LEVELPERIPH_9 13
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#define ESP32S2_CPUINT_LEVELPERIPH_10 17
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#define ESP32S2_CPUINT_LEVELPERIPH_11 18
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#define ESP32S2_CPUINT_LEVELPERIPH_12 19
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#define ESP32S2_CPUINT_LEVELPERIPH_13 20
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#define ESP32S2_CPUINT_LEVELPERIPH_14 21
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#define ESP32S2_CPUINT_LEVELPERIPH_15 23
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#define ESP32S2_CPUINT_LEVELPERIPH_16 24
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#define ESP32S2_CPUINT_LEVELPERIPH_17 25
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#define ESP32S2_CPUINT_LEVELPERIPH_18 26
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#define ESP32S2_CPUINT_LEVELPERIPH_19 27
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#define ESP32S2_CPUINT_LEVELPERIPH_20 31
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#define ESP32S2_CPUINT_NLEVELPERIPHS 21
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2022-01-12 20:23:07 +01:00
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#define ESP32S2_CPUINT_LEVELSET 0x8fbe333f
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2021-05-20 22:07:54 +02:00
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#define ESP32S2_CPUINT_EDGEPERIPH_0 10
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#define ESP32S2_CPUINT_EDGEPERIPH_1 22
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#define ESP32S2_CPUINT_EDGEPERIPH_2 28
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#define ESP32S2_CPUINT_EDGEPERIPH_3 30
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#define ESP32S2_CPUINT_NEDGEPERIPHS 4
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2022-01-12 20:23:07 +01:00
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#define ESP32S2_CPUINT_EDGESET 0x50400400
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2021-05-20 22:07:54 +02:00
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#define ESP32S2_CPUINT_NNMIPERIPHS 1
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2022-01-12 20:23:07 +01:00
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#define ESP32S2_CPUINT_NMISET 0x00004000
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2021-05-20 22:07:54 +02:00
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#define ESP32S2_CPUINT_MAC 0
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#define ESP32S2_CPUINT_TIMER0 6
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#define ESP32S2_CPUINT_SOFTWARE0 7
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#define ESP32S2_CPUINT_PROFILING 11
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#define ESP32S2_CPUINT_TIMER1 15
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#define ESP32S2_CPUINT_TIMER2 16
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#define ESP32S2_CPUINT_SOFTWARE1 29
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#define ESP32S2_CPUINT_NINTERNAL 6
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#define ESP32S2_NCPUINTS 32
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#define ESP32S2_CPUINT_MAX (ESP32S2_NCPUINTS - 1)
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2022-01-12 20:23:07 +01:00
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#define ESP32S2_CPUINT_PERIPHSET 0xdffe773f
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#define ESP32S2_CPUINT_INTERNALSET 0x200188c0
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2021-05-20 22:07:54 +02:00
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/* Priority 1: 0-10, 12-13, 17-18 (15)
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* Priority 2: 19-21 (3)
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* Priority 3: 11, 15, 22-23, 27, 29 (6)
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* Priority 4: 24-25, 28, 30 (4)
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* Priority 5: 16, 26, 31 (3)
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* Priority NMI: 14 (1)
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*/
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#define ESP32S2_INTPRI1_MASK 0x000637ff
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#define ESP32S2_INTPRI2_MASK 0x00380000
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#define ESP32S2_INTPRI3_MASK 0x28c08800
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#define ESP32S2_INTPRI4_MASK 0x53000000
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#define ESP32S2_INTPRI5_MASK 0x84010000
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#define ESP32S2_INTNMI_MASK 0x00004000
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H */
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