151 lines
6.9 KiB
C
151 lines
6.9 KiB
C
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/****************************************************************************
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* arch/xtensa/include/esp32s2/tie-asm.h
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* Compile-time assembler definitions dependent on CORE & TIE
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*
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* This header file contains assembly-language definitions (assembly
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* macros, etc.) for this specific Xtensa processor's TIE extensions
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* and options. It is customized to this Xtensa processor configuration.
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*
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* Customer ID=11657; Build=0x5fe96;
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* Copyright (c) 1999-2016 Cadence Design Systems Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H
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#define __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Selection parameter values for save-area save/restore macros: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
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| ((ccuse) & XTHAL_SAS_ANYCC) \
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| ((abi) & XTHAL_SAS_ANYABI) )
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/* Macro to store all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first
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* XCHAL_NCP_NUM_ATMPS registers are clobbered, the
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* remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger store sequence,
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* set to 1 if this is not the first in the sequence.
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* Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first
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* ptr in sequence) at which to store. Defaults to next
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* available space (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to store, as a
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* bitmask (see XTHAL_SAS_xxx constants). Defaults to all
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* registers.
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* alloc Select what category(ies) of registers to allocate; if
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* any category is selected here that is not in <select>,
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* space for the corresponding registers is skipped without
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* doing any store.
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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/* Optional global registers used by default by the compiler: */
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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rur.THREADPTR \at1 /* threadptr option */
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s32i \at1, \ptr, .Lxchal_ofs_+0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.endm /* xchal_ncp_store */
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/* Macro to load all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first
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* XCHAL_NCP_NUM_ATMPS registers are clobbered, the
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* remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger load sequence, set
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* to 1 if this is not the first in the sequence. Defaults
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* to 0.
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* ofs Offset from start of larger sequence (from value of first
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* ptr in sequence) at which to load. Defaults to next
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* available space (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to load, as a
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* bitmask (see XTHAL_SAS_xxx constants). Defaults to all
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* registers.
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* alloc Select what category(ies) of registers to allocate; if
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* any category is selected here that is not in <select>,
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* space for the corresponding registers is skipped without
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* doing any load.
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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/* Optional global registers used by default by the compiler: */
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wur.THREADPTR \at1 /* threadptr option */
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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.endm /* xchal_ncp_load */
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#define XCHAL_NCP_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H */
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