2011-02-25 19:46:06 +01:00
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README
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^^^^^^
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This README discusses issues unique to NuttX configurations for the
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Future Electronics Group NE64 /PoE Badge board based on the
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MC9S12NE64 hcs12 cpu.
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CONTENTS
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^^^^^^^^
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<20> MC9S12NE64 Features
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<20> NE64 Badge Pin Usage
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<20> Development Environment
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<20> NuttX Buildroot Toolchain
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<20> FreeScale HCS12 Serial Monitor
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<20> Soft Registers
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<20> HCS12/NE64BADGE-specific Configuration Options
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<20> Configurations
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MC9S12NE64 Features
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^^^^^^^^^^^^^^^^^^^
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<20> 16-bit HCS12 core
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- HCS12 CPU
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- Upward compatible with M68HC11 instruction set
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- Interrupt stacking and programmer<65>s model identical to M68HC11
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- Instruction queue
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- Enhanced indexed addressing
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- Memory map and interface (MMC)
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- Interrupt control (INT)
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- Background debug mode (BDM)
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- Enhanced debug12 module, including breakpoints and change-of-flow
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trace buffer (DBG)
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- Multiplexed expansion bus interface (MEBI) - available only in
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112-pin package version
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<20> Wakeup interrupt inputs
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- Up to 21 port bits available for wakeup interrupt function with
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digital filtering
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<20> Memory
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- 64K bytes of FLASH EEPROM
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- 8K bytes of RAM
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<20> Analog-to-digital converter (ATD)
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- One 8-channel module with 10-bit resolution
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- External conversion trigger capability
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<20> Timer module (TIM)
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- 4-channel timer
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- Each channel configurable as either input capture or output
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compare
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- Simple PWM mode
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- Modulo reset of timer counter
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- 16-bit pulse accumulator
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- External event counting
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- Gated time accumulation
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<20> Serial interfaces
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- Two asynchronous serial communications interface (SCI)
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- One synchronous serial peripheral interface (SPI)
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- One inter-IC bus (IIC)
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<20> Ethernet Media access controller (EMAC)
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- IEEE 802.3 compliant
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- Medium-independent interface (MII)
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- Full-duplex and half-duplex modes
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- Flow control using pause frames
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- MII management function
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- Address recognition
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- Frames with broadcast address are always accepted or always
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rejected
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- Exact match for single 48-bit individual (unicast) address
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- Hash (64-bit hash) check of group (multicast) addresses
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- Promiscuous mode
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<20> Ethertype filter
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<20> Loopback mode
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<20> Two receive and one transmit Ethernet buffer interfaces
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<20> Ethernet 10/100 Mbps transceiver (EPHY)
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- IEEE 802.3 compliant
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- Digital adaptive equalization
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- Half-duplex and full-duplex
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- Auto-negotiation next page ability
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- Baseline wander (BLW) correction
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- 125-MHz clock generator and timing recovery
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- Integrated wave-shaping circuitry
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- Loopback modes
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<20> CRG (clock and reset generator module)
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- Windowed COP watchdog
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- Real-time interrupt
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- Clock monitor
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- Pierce oscillator
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- Phase-locked loop clock frequency multiplier
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- Limp home mode in absence of external clock
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- 25-MHz crystal oscillator reference clock
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<20> Operating frequency
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- 50 MHz equivalent to 25 MHz bus speed for single chip
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- 32 MHz equivalent to 16 MHz bus speed in expanded bus modes
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<20> Internal 2.5-V regulator
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- Supports an input voltage range from 3.3 V <20> 5%
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- Low-power mode capability
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- Includes low-voltage reset (LVR) circuitry
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<20> 80-pin TQFP-EP or 112-pin LQFP package
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- Up to 70 I/O pins with 3.3 V input and drive capability (112-pin
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package)
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- Up to two dedicated 3.3 V input only lines (IRQ, XIRQ)
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<20> Development support
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- Single-wire background debug<75> mode (BDM)
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- On-chip hardware breakpoints
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- Enhanced DBG debug features
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NE64 Badge Pin Usage
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^^^^^^^^^^^^^^^^^^^^
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PIN PIN NAME BOARD SIGNAL NOTES
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--- ------------------- -------------- ----------------------
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44 RESET J3 RESET_L Also to SW3
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57 BKGD/MODC/TAGHI_B BDM BKGD CON6A
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2011-02-26 00:05:37 +01:00
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85 PAD0 VR1 Potentiometer
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2011-02-25 19:46:06 +01:00
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86 PAD1 J3 ANALOG_IN0 Not used on board
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87 PAD2 J3 ANALOG_IN1 " " " " "" " "
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88 PAD3 J3 ANALOG_IN2 " " " " "" " "
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89 PAD4 J3 ANALOG_IN3 " " " " "" " "
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70 PHY_TXP J7 TD+ RJ45 connector
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71 PHY_TXN J7 TD- RJ45 connector
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73 PHY_RXP J7 RD+ RJ45 connector
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74 PHY_RXN J7 RD- RJ45 connector
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2011-02-26 00:05:37 +01:00
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Ports A,B,E,K managed by the MEBI block
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---------------------------------------
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2011-02-25 19:46:06 +01:00
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60 PA0/ADDR8/DATA8 J3 ADDR_DATA8 Not used on board
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61 PA1/ADDR9/DATA9 J3 ADDR_DATA9 " " " " "" " "
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62 PA2/ADDR10/DATA10 J3 ADDR_DATA10 " " " " "" " "
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63 PA3/ADDR11/DATA11 J3 ADDR_DATA11 " " " " "" " "
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77 PA4/ADDR12/DATA12 J3 ADDR_DATA12 " " " " "" " "
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78 PA5/ADDR13/DATA13 J3 ADDR_DATA13 " " " " "" " "
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79 PA6/ADDR14/DATA14 J3 ADDR_DATA14 " " " " "" " "
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80 PA7/ADDR15/DATA15 J3 ADDR_DATA15 " " " " "" " "
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10 PB0/ADDR0/DATA0 J3 ADDR_DATA0 Not used on board
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11 PB1/ADDR1/DATA1 J3 ADDR_DATA1 " " " " "" " "
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12 PB2/ADDR2/DATA2 J3 ADDR_DATA2 " " " " "" " "
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13 PB3/ADDR3/DATA3 J3 ADDR_DATA3 " " " " "" " "
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16 PB4/ADDR4/DATA4 J3 ADDR_DATA4 " " " " "" " "
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17 PB5/ADDR5/DATA5 J3 ADDR_DATA5 " " " " "" " "
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18 PB6/ADDR6/DATA6 J3 ADDR_DATA6 " " " " "" " "
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19 PB7/ADDR7/DATA7 J3 ADDR_DATA7 " " " " "" " "
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56 PE0/XIRQ_B BUTTON1 SW1
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55 PE1/IRQ_B J3 IRQ Not used on board
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54 PE2/R_W J3 RW " " " " "" " "
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53 PE3/LSTRB_B/TAGLO_B J3 LSTRB " " " " "" " "
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41 PE4/ECLK J3 ECLK " " " " "" " "
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40 PE5/IPIPE0/MODA J3 MODA " " " " "" " "
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39 PE6/IPIPE1/MODB J3 MODB " " " " "" " "
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38 PE7/NOACC/XCLKS_B pulled low pulled low
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2011-02-26 00:05:37 +01:00
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97 PK0/XADR14 N/C N/C
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98 PK1/XADR15 N/C N/C
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99 PK2/XADR16 N/C N/C
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100 PK3/XADR17 N/C N/C
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103 PK4/XADR18 N/C N/C
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104 PK5/XADR19 N/C N/C
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105 PK6/XCS_B J3 XCS Not used on board
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106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " "
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Ports T,S,G,H,J,L managed by the PIM Block
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------------------------------------------
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2011-02-25 19:46:06 +01:00
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110 PT4/IOC1_4 J3 GPIO8 Not used on board
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109 PT5/IOC1_5 J3 GPIO9 " " " " "" " "
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108 PT6/IOC1_6 J3 GPIO10 " " " " "" " "
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107 PT7/IOC1_7 N/C N/C
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30 PS0/RXD0 RS232_RX Eventually maps to J2 RXD
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31 PS1/TXD0 RS232_TX Eventually maps to J2 TXD
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32 PS2/RXD1 J3&J4 UART_RX Not used on board
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33 PS3/TXD1 J3&J4 UART_TX " " " " "" " "
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34 PS4/MISO J3 SPI_MISO " " " " "" " "
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35 PS5/MOSI J3 SPI_MOSI " " " " "" " "
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36 PS6/SCK J3 SPI_CLOCK " " " " "" " "
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37 PS7/SS_B J3 SPI_SS " " " " "" " "
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2011-02-26 00:05:37 +01:00
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22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board
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23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " "
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24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " "
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25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " "
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26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " "
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27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " "
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28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " "
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29 PG7/KWG7 J3 GPIO7 " " " " "" " "
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2011-02-25 19:46:06 +01:00
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7 PH0/TXD0/KWH0 N/C N/C
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6 PH1/TXD1/KWH1 N/C N/C
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5 PH2/TXD2/KWH2 J4 XBEE_RESET Not used on board
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4 PH3/TXD3/KWH3 J4 XBEE_RSSI Not used on board
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3 PH4/TXCLK/KWH4 BUTTON2 SW2
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2 PH5/TXDV/KWH5 J5 XBEE_LOAD_H Not used on board
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1 PH6/TXER/KWH6 J4 XBEE_LOAD_L Not used on board
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2011-02-26 00:05:37 +01:00
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8 PJ0/MDC/KWJ0 LED1 D21, red
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9 PJ1/MDIO/KWJ1 LED2 D22, red
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20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board
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21 PJ3/COL/KWJ3 N/C
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112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board
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111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " "
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51 PL6/TXER/KWL6 N/C N/C
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52 PL5/TXDV/KWL5 N/C N/C
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58 PL4/COLLED Collision LED red
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59 PL3/DUPLED Full Duplex LED yellow
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81 PL2/SPDLED 100Mbps Speed LED yellow
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83 PL1/LNKLED Link Good LED green
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84 PL0/ACTLED Activity LED yellow
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2011-02-25 19:46:06 +01:00
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Development Environment
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^^^^^^^^^^^^^^^^^^^^^^^
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Either Linux or Cygwin on Windows can be used for the development
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environment. The source has been built only using the GNU toolchain
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(see below). Other toolchains will likely cause problems.
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NuttX Buildroot Toolchain
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^^^^^^^^^^^^^^^^^^^^^^^^^
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A GNU GCC-based toolchain is assumed. The files */setenv.sh should
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be modified to point to the correct path to the HC12 GCC toolchain (if
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different from the default in your PATH variable).
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If you have no HC12 toolchain, one can be downloaded from the NuttX
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SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
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This GNU toolchain builds and executes in the Linux or Cygwin
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environments.
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1. You must have already configured Nuttx in <some-dir>/nuttx.
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cd tools
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./configure.sh ne64badge/<sub-dir>
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2. Download the latest buildroot package into <some-dir>
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3. unpack the buildroot tarball. The resulting directory may
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have versioning information on it like buildroot-x.y.z. If so,
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rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
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4. cd <some-dir>/buildroot
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5. cp configs/m9s12x-defconfig-3.3.6 .config
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6. make oldconfig
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7. make
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If the make fails because it can't find the file to download, you may
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have to locate the file on the internet and download it into the archives/
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directory manually. For example, binutils-2.18 can be found here:
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http://ftp.gnu.org/gnu/binutils/
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8. Edit setenv.h, if necessary, so that the PATH variable includes
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the path to the newly built binaries.
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See the file configs/README.txt in the buildroot source tree. That has more
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detailed PLUS some special instructions that you will need to follow if you are
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building a Cortex-M3 toolchain for Cygwin under Windows.
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FreeScale HCS12 Serial Monitor
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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General:
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The NuttX HCS12 port is configured to use the Freescale HCS serial
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monitor. This monitor supports primitive debug commands that allow
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FLASH/EEPROM programming and debugging through an RS-232 serial
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interface. The serial monior is 2Kb in size and resides in FLASH at
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addresses 0xf800-0xffff. The monitor does not use any RAM other than
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the stack itself.
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AN2458
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The serial monitor is described in detail in Freescale Application
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Note AN2458.pdf.
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COP:
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The serial monitor uses the COP for the cold reset function and should
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not be used by the application without some precautions (see AN2458).
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Clocking:
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The serial monitor sets the operating frequency to 24 MHz. This is
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not altered by the NuttX start-up; doing so would interfere with the
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operation of the serial monitor.
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Memory Configuration:
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Registers:
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<20> Register space is located at 0x0000<30>0x03ff.
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FLASH:
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<20> FLASH memory is any address greater than 0x4000. All paged
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addresses are assumed to be FLASH memory.
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<20> Application code should exclude the 0xf780<38>0xff7f memory.
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SRAM:
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<20> RAM ends at 0x3FFF and builds down to the limit of the device<63>s
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available RAM.
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<20> The serial monitor's stack pointer is set to the end of RAM+1
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(0x4000).
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EEPROM:
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<20> EEPROM (if the target device has any) is limited to the available
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space between the registers and the RAM (0x0400<30>to start of RAM).
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External Devices:
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<20> External devices attached to the multiplexed external bus
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interface are not supported
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Serial Communications:
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The serial monitor uses RS-232 serial communications through SCI0 at
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115,200 baud. The monitor must have exclusive use of this interface.
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Access to the serial port is available through a monitor jump table.
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Interrrupts:
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The serial monitor redirects interrupt vectors to an unprotected
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portion of FLASH just before the protected monitor program
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(0xf780<38>0xf7fe). The monitor will automatically redirect vector
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programming operations to these user vectors. The user code should
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therefore keep the normal (non-monitor) vector locations
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(0xff80<38>0xfffe).
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Soft Registers
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^^^^^^^^^^^^^^
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The mc68hcs12 compilation is prone to errors like the following:
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CC: lib_b16sin.c
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lib_b16sin.c: In function `b16sin':
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lib_b16sin.c:110: error: unable to find a register to spill in class `S_REGS'
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lib_b16sin.c:110: error: this is the insn:
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(insn:HI 41 46 44 8 (parallel [
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(set (subreg:SI (reg:DI 58 [ rad ]) 4)
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(reg/v:SI 54 [ rad ]))
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(clobber (scratch:HI))
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]) 20 {movsi_internal} (insn_list 46 (nil))
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(expr_list:REG_UNUSED (scratch:HI)
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(expr_list:REG_NO_CONFLICT (reg/v:SI 54 [ rad ])
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(nil))))
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lib_b16sin.c:110: confused by earlier errors, bailing out
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There are several ways that this error could be fixed:
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1. Increase the number of soft registers (i.e., "fake" registers defined
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at fixed memory locations). This can be done by adding something like
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-msoft-reg-count=4 to the CFLAGS. This approach was not taken
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because:
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- This slows hcs12 performance
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- All of these soft registers wouil have to be saved and restored
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on every interrupt and context switch.
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2. Lowering the optimization level by dropping -Os to -O2 or, more likely,
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by removing -fomit-frame-pointer. Also not desireable becauase 99% of the
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files that do not have this problem also increase in size. Special case
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compilation with reduced optimization levels just for the files that need
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it could be done, but this would complicate the make system.
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3. Restructuring files to reduce the complexity. If you add local variables
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to hold intermediate computational results, this error can be eliminated.
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This is the approach taken in NuttX. It has disadvantages only in that
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(1) it takes some effort and good guessing to eliminate the problem, and (2)
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the problem is not really eliminated -- it can and will re-occur when files
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are changed or new files are added.
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4. Many files are built that are needed by DEM09S12NE64. Another very simple
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option if those problem files are needed is to just remove the offending
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files from the Make.defs file so that they no longer cause a problem.
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HCS12/NE64BADGE-specific Configuration Options
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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CONFIG_ARCH - Identifies the arch/ subdirectory. This should
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be set to:
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CONFIG_ARCH=hc
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CONFIG_ARCH_family - For use in C code:
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CONFIG_ARCH_HC=y
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CONFIG_ARCH_architecture - For use in C code:
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CONFIG_ARCH_HCS12=y
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CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
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CONFIG_ARCH_CHIP=mc92s12nec64
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CONFIG_ARCH_CHIP_name - For use in C code
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CONFIG_ARCH_CHIP_MCS92S12NEC64
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CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
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hence, the board that supports the particular chip or SoC.
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CONFIG_ARCH_BOARD=ne64badge
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CONFIG_ARCH_BOARD_name - For use in C code
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CONFIG_ARCH_BOARD_NE64BADGE (for the Future Electronics Group NE64 Badge)
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CONFIG_ENDIAN_BIG - define if big endian (default is little
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endian)
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CONFIG_DRAM_SIZE - Describes the installed RAM.
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CONFIG_DRAM_START - The start address of installed RAM
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CONFIG_DRAM_END - Should be (CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
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have LEDs
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
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cause a 100 second delay during boot-up. This 100 second delay
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serves no purpose other than it allows you to calibratre
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CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
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the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
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the delay actually is 100 seconds.
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2011-02-26 17:55:39 +01:00
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GPIO Interrupts
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CONFIG_GPIO_IRQ - Enable general support for GPIO IRQs
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CONFIG_HCS12_PORTG_INTS - Enable PortG IRQs
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CONFIG_HCS12_PORTH_INTS - Enable PortH IRQs
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CONFIG_HCS12_PORTJ_INTS - Enable PortJ IRQs
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2011-02-25 19:46:06 +01:00
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HCS12 build options:
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CONFIG_HCS12_SERIALMON - Indicates that the target systems uses
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the Freescale serial bootloader.
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CONFIG_HCS12_NONBANKED - Indicates that the target systems does not
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support banking. Only short calls are made; one fixed page is
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presented the the paging window. Only 48Kb of FLASH is usable
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in this configuration: pages 3e, 3d, then 3f will appear as a
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contiguous address space in memory.
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HCS12 Sub-system support
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CONFIG_HCS12_SCI0
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CONFIG_HCS12_SCI1
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HCS12 specific device driver settings:
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CONFIG_SCIn_SERIAL_CONSOLE - selects SCIn for the console and ttys0
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(default is the SCI0).
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CONFIG_SCIn_RXBUFSIZE - Characters are buffered as received.
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This specific the size of the receive buffer
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CONFIG_SCIn_TXBUFSIZE - Characters are buffered before
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being sent. This specific the size of the transmit buffer
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CONFIG_SCIn_BAUD - The configure BAUD of the UART.
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CONFIG_SCIn_BITS - The number of bits. Must be either 7 or 8.
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CONFIG_SCIn_PARTIY - 0=no parity, 1=odd parity, 2=even parity, 3=mark 1, 4=space 0
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CONFIG_SCIn_2STOP - Two stop bits
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Configurations
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^^^^^^^^^^^^^^
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Each Freescale HCS12 configuration is maintained in a sudirectory and
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can be selected as follow:
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cd tools
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./configure.sh ne64badge/<subdir>
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cd -
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. ./setenv.sh
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Where <subdir> is one of the following:
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ostest:
|
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This configuration directory, performs a simple OS test using
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examples/ostest.
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