2011-03-10 01:58:10 +01:00
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/****************************************************************************
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* drivers/serial/uart_16550.c
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* Serial driver for 16550 UART
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*
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2018-08-26 19:17:33 +02:00
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* Copyright (C) 2011, 2013, 2017-2018 Gregory Nutt. All rights reserved.
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2012-07-15 16:56:25 +02:00
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* Author: Gregory Nutt <gnutt@nuttx.org>
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2011-03-10 01:58:10 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <unistd.h>
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#include <semaphore.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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2012-03-21 20:47:23 +01:00
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#include <nuttx/serial/serial.h>
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2012-03-21 19:01:07 +01:00
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#include <nuttx/fs/ioctl.h>
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2012-03-21 20:47:23 +01:00
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#include <nuttx/serial/uart_16550.h>
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2011-03-10 01:58:10 +01:00
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#include <arch/board/board.h>
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2011-03-10 05:13:44 +01:00
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#ifdef CONFIG_16550_UART
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2011-03-10 01:58:10 +01:00
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/****************************************************************************
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* Pre-processor definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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2011-03-10 05:13:44 +01:00
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struct u16550_s
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2011-03-10 01:58:10 +01:00
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{
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uart_addrwidth_t uartbase; /* Base address of UART registers */
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2011-03-10 01:58:10 +01:00
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uint32_t baud; /* Configured baud */
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uint32_t uartclk; /* UART clock frequency */
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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uart_datawidth_t ier; /* Saved IER value */
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uint8_t irq; /* IRQ associated with this UART */
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2011-03-10 01:58:10 +01:00
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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2018-08-26 19:37:16 +02:00
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#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
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bool flow; /* flow control (RTS/CTS) enabled */
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#endif
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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2017-02-27 17:44:13 +01:00
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static int u16550_setup(FAR struct uart_dev_s *dev);
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static void u16550_shutdown(FAR struct uart_dev_s *dev);
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static int u16550_attach(FAR struct uart_dev_s *dev);
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2017-04-20 14:50:01 +02:00
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static void u16550_detach(FAR struct uart_dev_s *dev);
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2017-02-27 17:44:13 +01:00
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static int u16550_interrupt(int irq, FAR void *context, FAR void *arg);
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static int u16550_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
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static int u16550_receive(FAR struct uart_dev_s *dev, uint32_t *status);
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static void u16550_rxint(FAR struct uart_dev_s *dev, bool enable);
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static bool u16550_rxavailable(FAR struct uart_dev_s *dev);
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2018-08-26 19:37:16 +02:00
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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static bool u16550_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
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bool upper);
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#endif
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2018-08-26 19:20:15 +02:00
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#ifdef CONFIG_SERIAL_DMA
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static void u16550_dmasend(FAR struct uart_dev_s *dev);
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static void u16550_dmareceive(FAR struct uart_dev_s *dev);
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static void u16550_dmarxfree(FAR struct uart_dev_s *dev);
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static void u16550_dmatxavail(FAR struct uart_dev_s *dev);
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#endif
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2017-02-27 17:44:13 +01:00
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static void u16550_send(FAR struct uart_dev_s *dev, int ch);
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static void u16550_txint(FAR struct uart_dev_s *dev, bool enable);
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static bool u16550_txready(FAR struct uart_dev_s *dev);
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static bool u16550_txempty(FAR struct uart_dev_s *dev);
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2011-03-10 01:58:10 +01:00
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/****************************************************************************
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2016-02-22 01:08:58 +01:00
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* Private Data
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2011-03-10 01:58:10 +01:00
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****************************************************************************/
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2013-02-27 23:24:49 +01:00
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static const struct uart_ops_s g_uart_ops =
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2011-03-10 01:58:10 +01:00
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{
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2011-03-10 05:13:44 +01:00
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.setup = u16550_setup,
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.shutdown = u16550_shutdown,
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.attach = u16550_attach,
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.detach = u16550_detach,
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.ioctl = u16550_ioctl,
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.receive = u16550_receive,
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.rxint = u16550_rxint,
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.rxavailable = u16550_rxavailable,
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2014-05-08 17:00:33 +02:00
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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2018-08-26 19:37:16 +02:00
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.rxflowcontrol = u16550_rxflowcontrol,
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2018-08-26 19:20:15 +02:00
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#endif
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#ifdef CONFIG_SERIAL_DMA
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.dmasend = u16550_dmasend,
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.dmareceive = u16550_dmareceive,
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.dmarxfree = u16550_dmarxfree,
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.dmatxavail = u16550_dmatxavail,
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2014-05-08 17:00:33 +02:00
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#endif
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2011-03-10 05:13:44 +01:00
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.send = u16550_send,
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.txint = u16550_txint,
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.txready = u16550_txready,
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.txempty = u16550_txempty,
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2011-03-10 01:58:10 +01:00
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};
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/* I/O buffers */
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#ifdef CONFIG_16550_UART0
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2012-09-05 19:20:19 +02:00
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static char g_uart0rxbuffer[CONFIG_16550_UART0_RXBUFSIZE];
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static char g_uart0txbuffer[CONFIG_16550_UART0_TXBUFSIZE];
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2011-03-10 01:58:10 +01:00
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#endif
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#ifdef CONFIG_16550_UART1
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2012-09-05 19:20:19 +02:00
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static char g_uart1rxbuffer[CONFIG_16550_UART1_RXBUFSIZE];
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static char g_uart1txbuffer[CONFIG_16550_UART1_TXBUFSIZE];
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2011-03-10 01:58:10 +01:00
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#endif
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#ifdef CONFIG_16550_UART2
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2012-09-05 19:20:19 +02:00
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static char g_uart2rxbuffer[CONFIG_16550_UART2_RXBUFSIZE];
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static char g_uart2txbuffer[CONFIG_16550_UART2_TXBUFSIZE];
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2011-03-10 01:58:10 +01:00
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#endif
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#ifdef CONFIG_16550_UART3
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2012-09-05 19:20:19 +02:00
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static char g_uart3rxbuffer[CONFIG_16550_UART3_RXBUFSIZE];
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static char g_uart3txbuffer[CONFIG_16550_UART3_TXBUFSIZE];
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2011-03-10 01:58:10 +01:00
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#endif
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2018-08-26 19:17:33 +02:00
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/* This describes the state of the 16550 uart0 port. */
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2011-03-10 01:58:10 +01:00
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#ifdef CONFIG_16550_UART0
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2011-03-10 05:13:44 +01:00
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static struct u16550_s g_uart0priv =
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2011-03-10 01:58:10 +01:00
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{
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.uartbase = CONFIG_16550_UART0_BASE,
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2012-09-05 19:20:19 +02:00
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.baud = CONFIG_16550_UART0_BAUD,
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2011-03-10 01:58:10 +01:00
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.uartclk = CONFIG_16550_UART0_CLOCK,
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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.irq = CONFIG_16550_UART0_IRQ,
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2012-09-05 19:20:19 +02:00
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.parity = CONFIG_16550_UART0_PARITY,
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.bits = CONFIG_16550_UART0_BITS,
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.stopbits2 = CONFIG_16550_UART0_2STOP,
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2018-08-26 19:37:16 +02:00
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#if defined(CONFIG_16550_UART0_IFLOWCONTROL) || defined(CONFIG_16550_UART0_OFLOWCONTROL)
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.flow = true,
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#endif
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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};
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static uart_dev_t g_uart0port =
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{
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.recv =
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{
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2012-09-05 19:20:19 +02:00
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.size = CONFIG_16550_UART0_RXBUFSIZE,
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2011-03-10 01:58:10 +01:00
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.buffer = g_uart0rxbuffer,
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},
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.xmit =
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{
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2012-09-05 19:20:19 +02:00
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.size = CONFIG_16550_UART0_TXBUFSIZE,
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2011-03-10 01:58:10 +01:00
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.buffer = g_uart0txbuffer,
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},
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.ops = &g_uart_ops,
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.priv = &g_uart0priv,
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};
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#endif
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2018-08-26 19:17:33 +02:00
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/* This describes the state of the 16550 uart1 port. */
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2011-03-10 01:58:10 +01:00
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#ifdef CONFIG_16550_UART1
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2011-03-10 05:13:44 +01:00
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static struct u16550_s g_uart1priv =
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2011-03-10 01:58:10 +01:00
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{
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.uartbase = CONFIG_16550_UART1_BASE,
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2012-09-05 19:20:19 +02:00
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.baud = CONFIG_16550_UART1_BAUD,
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2011-03-10 01:58:10 +01:00
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.uartclk = CONFIG_16550_UART1_CLOCK,
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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.irq = CONFIG_16550_UART1_IRQ,
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2012-09-05 19:20:19 +02:00
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.parity = CONFIG_16550_UART1_PARITY,
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.bits = CONFIG_16550_UART1_BITS,
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.stopbits2 = CONFIG_16550_UART1_2STOP,
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2019-01-27 17:56:23 +01:00
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#if defined(CONFIG_16550_UART1_IFLOWCONTROL) || defined(CONFIG_16550_UART1_OFLOWCONTROL)
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2018-08-26 19:37:16 +02:00
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.flow = true,
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#endif
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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};
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static uart_dev_t g_uart1port =
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{
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.recv =
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{
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2012-09-05 19:20:19 +02:00
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.size = CONFIG_16550_UART1_RXBUFSIZE,
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2011-03-10 01:58:10 +01:00
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.buffer = g_uart1rxbuffer,
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},
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.xmit =
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{
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2012-09-05 19:20:19 +02:00
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.size = CONFIG_16550_UART1_TXBUFSIZE,
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2011-03-10 01:58:10 +01:00
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.buffer = g_uart1txbuffer,
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},
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.ops = &g_uart_ops,
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.priv = &g_uart1priv,
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};
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#endif
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2018-08-26 19:17:33 +02:00
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/* This describes the state of the 16550 uart1 port. */
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2011-03-10 01:58:10 +01:00
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#ifdef CONFIG_16550_UART2
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2011-03-10 05:13:44 +01:00
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static struct u16550_s g_uart2priv =
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2011-03-10 01:58:10 +01:00
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{
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.uartbase = CONFIG_16550_UART2_BASE,
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2012-09-05 19:20:19 +02:00
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.baud = CONFIG_16550_UART2_BAUD,
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2011-03-10 01:58:10 +01:00
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.uartclk = CONFIG_16550_UART2_CLOCK,
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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.irq = CONFIG_16550_UART2_IRQ,
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2011-03-10 05:13:44 +01:00
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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2012-09-05 19:20:19 +02:00
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.parity = CONFIG_16550_UART2_PARITY,
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.bits = CONFIG_16550_UART2_BITS,
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.stopbits2 = CONFIG_16550_UART2_2STOP,
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2018-08-26 19:37:16 +02:00
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#if defined(CONFIG_16550_UART2_IFLOWCONTROL) || defined(CONFIG_16550_UART2_OFLOWCONTROL)
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.flow = true,
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#endif
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2011-03-10 05:13:44 +01:00
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#endif
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2011-03-10 01:58:10 +01:00
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};
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static uart_dev_t g_uart2port =
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{
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.recv =
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{
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2012-09-05 19:20:19 +02:00
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.size = CONFIG_16550_UART2_RXBUFSIZE,
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2011-03-10 01:58:10 +01:00
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.buffer = g_uart2rxbuffer,
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},
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.xmit =
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{
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2012-09-05 19:20:19 +02:00
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.size = CONFIG_16550_UART2_TXBUFSIZE,
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2011-03-10 01:58:10 +01:00
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.buffer = g_uart2txbuffer,
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},
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.ops = &g_uart_ops,
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.priv = &g_uart2priv,
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};
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#endif
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2018-08-26 19:17:33 +02:00
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/* This describes the state of the 16550 uart1 port. */
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2011-03-10 01:58:10 +01:00
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#ifdef CONFIG_16550_UART3
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2011-03-10 05:13:44 +01:00
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static struct u16550_s g_uart3priv =
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2011-03-10 01:58:10 +01:00
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{
|
|
|
|
.uartbase = CONFIG_16550_UART3_BASE,
|
2011-03-10 05:13:44 +01:00
|
|
|
#ifndef CONFIG_16550_SUPRESS_CONFIG
|
2012-09-05 19:20:19 +02:00
|
|
|
.baud = CONFIG_16550_UART3_BAUD,
|
2011-03-10 01:58:10 +01:00
|
|
|
.uartclk = CONFIG_16550_UART3_CLOCK,
|
2011-03-10 05:13:44 +01:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
.irq = CONFIG_16550_UART3_IRQ,
|
2011-03-10 05:13:44 +01:00
|
|
|
#ifndef CONFIG_16550_SUPRESS_CONFIG
|
2012-09-05 19:20:19 +02:00
|
|
|
.parity = CONFIG_16550_UART3_PARITY,
|
|
|
|
.bits = CONFIG_16550_UART3_BITS,
|
|
|
|
.stopbits2 = CONFIG_16550_UART3_2STOP,
|
2018-08-26 19:37:16 +02:00
|
|
|
#if defined(CONFIG_16550_UART3_IFLOWCONTROL) || defined(CONFIG_16550_UART3_OFLOWCONTROL)
|
|
|
|
.flow = true,
|
|
|
|
#endif
|
2011-03-10 05:13:44 +01:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static uart_dev_t g_uart3port =
|
|
|
|
{
|
|
|
|
.recv =
|
|
|
|
{
|
2012-09-05 19:20:19 +02:00
|
|
|
.size = CONFIG_16550_UART3_RXBUFSIZE,
|
2011-03-10 01:58:10 +01:00
|
|
|
.buffer = g_uart3rxbuffer,
|
|
|
|
},
|
|
|
|
.xmit =
|
|
|
|
{
|
2012-09-05 19:20:19 +02:00
|
|
|
.size = CONFIG_16550_UART3_TXBUFSIZE,
|
2011-03-10 01:58:10 +01:00
|
|
|
.buffer = g_uart3txbuffer,
|
|
|
|
},
|
|
|
|
.ops = &g_uart_ops,
|
|
|
|
.priv = &g_uart3priv,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2018-08-26 19:17:33 +02:00
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
/* Which UART with be tty0/console and which tty1? tty2? tty3? */
|
|
|
|
|
2018-08-26 19:17:33 +02:00
|
|
|
#ifdef CONFIG_16550_SERIAL_DISABLE_REORDERING
|
|
|
|
|
|
|
|
# if defined(CONFIG_16550_UART0_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart0port /* UART0=console */
|
|
|
|
# elif defined(CONFIG_16550_UART1_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart1port /* UART1=console */
|
|
|
|
# elif defined(CONFIG_16550_UART2_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart2port /* UART2=console */
|
|
|
|
# elif defined(CONFIG_16550_UART3_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart3port /* UART3=console */
|
|
|
|
# endif
|
|
|
|
|
|
|
|
# ifdef CONFIG_16550_UART0
|
|
|
|
# define TTYS0_DEV g_uart0port
|
|
|
|
# endif
|
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
# ifdef CONFIG_16550_UART1
|
2018-08-26 19:17:33 +02:00
|
|
|
# define TTYS1_DEV g_uart1port
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
2018-08-26 19:17:33 +02:00
|
|
|
|
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS2_DEV g_uart2port
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
2018-08-26 19:17:33 +02:00
|
|
|
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS3_DEV g_uart3port
|
|
|
|
# endif
|
|
|
|
|
|
|
|
#else /* CONFIG_16550_SERIAL_DISABLE_REORDERING */
|
|
|
|
|
|
|
|
/* Which UART with be tty0/console and which tty1? tty2? tty3? */
|
|
|
|
|
|
|
|
# if defined(CONFIG_16550_UART0_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart0port /* UART0=console */
|
|
|
|
# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# ifdef CONFIG_16550_UART1
|
2018-08-26 19:17:33 +02:00
|
|
|
# define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS3_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2;UART3=ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS3_DEV /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS;No ttyS3 */
|
|
|
|
# endif
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART3=ttys2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1;No ttyS3 */
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS1_DEV g_uart3port /* UART0=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS2_DEV /* No ttyS2 */
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# endif
|
2018-08-26 19:17:33 +02:00
|
|
|
# elif defined(CONFIG_16550_UART1_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart1port /* UART1=console */
|
|
|
|
# define TTYS0_DEV g_uart1port /* UART1=ttyS0 */
|
2019-01-27 17:52:09 +01:00
|
|
|
# ifdef CONFIG_16550_UART0
|
2018-08-26 19:17:33 +02:00
|
|
|
# define TTYS1_DEV g_uart0port /* UART1=ttyS0;UART0=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS2_DEV g_uart2port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2 */
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS3_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2;UART3=ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS3_DEV /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS;No ttyS3 */
|
|
|
|
# endif
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART1=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS1_DEV g_uart2port /* UART1=ttyS0;UART2=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART1=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS1_DEV g_uart3port /* UART1=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS1_DEV /* UART1=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS2_DEV /* No ttyS2 */
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# endif
|
2018-08-26 19:17:33 +02:00
|
|
|
# elif defined(CONFIG_16550_UART2_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart2port /* UART2=console */
|
|
|
|
# define TTYS0_DEV g_uart2port /* UART2=ttyS0 */
|
2019-01-27 17:52:09 +01:00
|
|
|
# ifdef CONFIG_16550_UART0
|
2018-08-26 19:17:33 +02:00
|
|
|
# define TTYS1_DEV g_uart0port /* UART2=ttyS0;UART0=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART1
|
|
|
|
# define TTYS2_DEV g_uart1port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2 */
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS3_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2;UART3=ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS3_DEV /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */
|
|
|
|
# endif
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART2=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART1
|
|
|
|
# define TTYS1_DEV g_uart1port /* UART2=ttyS0;UART1=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART1=ttyS1;UART3=ttyS2 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART2=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART3
|
|
|
|
# define TTYS1_DEV g_uart3port /* UART2=ttyS0;UART3=ttyS1;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS1_DEV /* UART2=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS2_DEV /* No ttyS2 */
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# endif
|
2018-08-26 19:17:33 +02:00
|
|
|
# elif defined(CONFIG_16550_UART3_SERIAL_CONSOLE)
|
|
|
|
# define CONSOLE_DEV g_uart3port /* UART3=console */
|
|
|
|
# define TTYS0_DEV g_uart3port /* UART3=ttyS0 */
|
2019-01-27 17:52:09 +01:00
|
|
|
# ifdef CONFIG_16550_UART0
|
2018-08-26 19:17:33 +02:00
|
|
|
# define TTYS1_DEV g_uart0port /* UART3=ttyS0;UART0=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART1
|
|
|
|
# define TTYS2_DEV g_uart1port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2 */
|
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS3_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2;UART2=ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS3_DEV /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */
|
|
|
|
# endif
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART2=ttys2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART3=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART1
|
|
|
|
# define TTYS1_DEV g_uart1port /* UART3=ttyS0;UART1=ttyS1 */
|
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART1=ttyS1;UART2=ttyS2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS2_DEV /* UART3=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# else
|
2018-08-26 19:17:33 +02:00
|
|
|
# ifdef CONFIG_16550_UART2
|
|
|
|
# define TTYS1_DEV g_uart2port /* UART3=ttyS0;UART2=ttyS1;No ttyS3;No ttyS3 */
|
|
|
|
# undef TTYS3_DEV /* UART3=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# else
|
|
|
|
# undef TTYS1_DEV /* UART3=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
|
|
|
|
# endif
|
|
|
|
# undef TTYS2_DEV /* No ttyS2 */
|
|
|
|
# undef TTYS3_DEV /* No ttyS3 */
|
2011-03-10 01:58:10 +01:00
|
|
|
# endif
|
|
|
|
# endif
|
|
|
|
# endif
|
2018-08-26 19:17:33 +02:00
|
|
|
|
|
|
|
#endif /* CONFIG_16550_SERIAL_DISABLE_REORDERING */
|
2011-03-10 01:58:10 +01:00
|
|
|
|
2017-09-30 20:59:33 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Private Functions
|
|
|
|
****************************************************************************/
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_serialin
|
2011-03-10 01:58:10 +01:00
|
|
|
****************************************************************************/
|
|
|
|
|
2015-10-10 18:41:00 +02:00
|
|
|
static inline uart_datawidth_t u16550_serialin(FAR struct u16550_s *priv, int offset)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2018-08-26 19:17:33 +02:00
|
|
|
#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
|
|
|
|
return *((FAR volatile uart_addrwidth_t *)priv->uartbase + offset);
|
|
|
|
#else
|
2011-03-10 01:58:10 +01:00
|
|
|
return uart_getreg(priv->uartbase, offset);
|
2018-08-26 19:17:33 +02:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_serialout
|
2011-03-10 01:58:10 +01:00
|
|
|
****************************************************************************/
|
|
|
|
|
2015-10-10 18:41:00 +02:00
|
|
|
static inline void u16550_serialout(FAR struct u16550_s *priv, int offset,
|
|
|
|
uart_datawidth_t value)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2018-08-26 19:17:33 +02:00
|
|
|
#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
|
|
|
|
*((FAR volatile uart_addrwidth_t *)priv->uartbase + offset) = value;
|
|
|
|
#else
|
2011-03-10 01:58:10 +01:00
|
|
|
uart_putreg(priv->uartbase, offset, value);
|
2018-08-26 19:17:33 +02:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_disableuartint
|
2011-03-10 01:58:10 +01:00
|
|
|
****************************************************************************/
|
|
|
|
|
2015-10-10 18:41:00 +02:00
|
|
|
static inline void u16550_disableuartint(FAR struct u16550_s *priv,
|
|
|
|
FAR uart_datawidth_t *ier)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
|
|
|
if (ier)
|
|
|
|
{
|
|
|
|
*ier = priv->ier & UART_IER_ALLIE;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->ier &= ~UART_IER_ALLIE;
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_IER_OFFSET, priv->ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_restoreuartint
|
2011-03-10 01:58:10 +01:00
|
|
|
****************************************************************************/
|
|
|
|
|
2017-09-30 20:59:33 +02:00
|
|
|
static inline void u16550_restoreuartint(FAR struct u16550_s *priv,
|
|
|
|
uint32_t ier)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
|
|
|
priv->ier |= ier & UART_IER_ALLIE;
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_IER_OFFSET, priv->ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_enablebreaks
|
2011-03-10 01:58:10 +01:00
|
|
|
****************************************************************************/
|
|
|
|
|
2017-09-30 20:59:33 +02:00
|
|
|
static inline void u16550_enablebreaks(FAR struct u16550_s *priv,
|
|
|
|
bool enable)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2011-03-10 05:13:44 +01:00
|
|
|
uint32_t lcr = u16550_serialin(priv, UART_LCR_OFFSET);
|
2016-05-05 19:30:47 +02:00
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
lcr |= UART_LCR_BRK;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
lcr &= ~UART_LCR_BRK;
|
|
|
|
}
|
2016-05-05 19:30:47 +02:00
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_LCR_OFFSET, lcr);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
2017-09-30 20:59:33 +02:00
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_divisor
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
2018-02-01 19:03:55 +01:00
|
|
|
* Description:
|
2011-03-10 01:58:10 +01:00
|
|
|
* Select a divider to produce the BAUD from the UART_CLK.
|
|
|
|
*
|
|
|
|
* BAUD = UART_CLK / (16 * DL), or
|
|
|
|
* DIV = UART_CLK / BAUD / 16
|
|
|
|
*
|
|
|
|
* Ignoring the fractional divider for now.
|
|
|
|
*
|
2017-09-30 20:59:33 +02:00
|
|
|
****************************************************************************/
|
2011-03-10 01:58:10 +01:00
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
#ifndef CONFIG_16550_SUPRESS_CONFIG
|
2015-10-10 18:41:00 +02:00
|
|
|
static inline uint32_t u16550_divisor(FAR struct u16550_s *priv)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2011-03-10 05:13:44 +01:00
|
|
|
return (priv->uartclk + (priv->baud << 3)) / (priv->baud << 4);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
2011-03-10 05:13:44 +01:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_setup
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure the UART baud, bits, parity, fifos, etc. This
|
|
|
|
* method is called the first time that the serial port is
|
|
|
|
* opened.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-09-30 20:59:33 +02:00
|
|
|
static int u16550_setup(FAR struct uart_dev_s *dev)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
|
|
|
#ifndef CONFIG_16550_SUPRESS_CONFIG
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 01:58:10 +01:00
|
|
|
uint16_t div;
|
|
|
|
uint32_t lcr;
|
2018-08-26 19:37:16 +02:00
|
|
|
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
|
|
|
uint32_t mcr;
|
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Clear fifos */
|
|
|
|
|
2015-10-10 18:41:00 +02:00
|
|
|
u16550_serialout(priv, UART_FCR_OFFSET,
|
|
|
|
(UART_FCR_RXRST | UART_FCR_TXRST));
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Set trigger */
|
|
|
|
|
2015-10-10 18:41:00 +02:00
|
|
|
u16550_serialout(priv, UART_FCR_OFFSET,
|
|
|
|
(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8));
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Set up the IER */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
priv->ier = u16550_serialin(priv, UART_IER_OFFSET);
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Set up the LCR */
|
|
|
|
|
|
|
|
lcr = 0;
|
|
|
|
switch (priv->bits)
|
|
|
|
{
|
|
|
|
case 5 :
|
2015-07-31 19:19:54 +02:00
|
|
|
lcr |= UART_LCR_WLS_5BIT;
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 6 :
|
2015-07-31 19:19:54 +02:00
|
|
|
lcr |= UART_LCR_WLS_6BIT;
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 7 :
|
|
|
|
lcr |= UART_LCR_WLS_7BIT;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
case 8 :
|
2015-07-31 19:19:54 +02:00
|
|
|
lcr |= UART_LCR_WLS_8BIT;
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->stopbits2)
|
|
|
|
{
|
|
|
|
lcr |= UART_LCR_STB;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->parity == 1)
|
|
|
|
{
|
|
|
|
lcr |= UART_LCR_PEN;
|
|
|
|
}
|
|
|
|
else if (priv->parity == 2)
|
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
lcr |= (UART_LCR_PEN | UART_LCR_EPS);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Enter DLAB=1 */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Set the BAUD divisor */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
div = u16550_divisor(priv);
|
|
|
|
u16550_serialout(priv, UART_DLM_OFFSET, div >> 8);
|
|
|
|
u16550_serialout(priv, UART_DLL_OFFSET, div & 0xff);
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Clear DLAB */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_LCR_OFFSET, lcr);
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Configure the FIFOs */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_FCR_OFFSET,
|
2015-10-10 18:41:00 +02:00
|
|
|
(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST |
|
|
|
|
UART_FCR_FIFOEN));
|
2018-08-26 19:37:16 +02:00
|
|
|
|
|
|
|
/* Set up the auto flow control */
|
|
|
|
|
|
|
|
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
|
|
|
mcr = u16550_serialin(priv, UART_MCR_OFFSET);
|
|
|
|
if (priv->flow)
|
|
|
|
{
|
|
|
|
mcr |= UART_MCR_AFCE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
mcr &= ~UART_MCR_AFCE;
|
|
|
|
}
|
|
|
|
|
2018-11-08 17:21:16 +01:00
|
|
|
mcr |= UART_MCR_RTS;
|
|
|
|
|
2018-08-26 19:37:16 +02:00
|
|
|
u16550_serialout(priv, UART_MCR_OFFSET, mcr);
|
|
|
|
#endif /* defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) */
|
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
#endif
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_shutdown
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Disable the UART. This method is called when the serial
|
|
|
|
* port is closed
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static void u16550_shutdown(struct uart_dev_s *dev)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_disableuartint(priv, NULL);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_attach
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure the UART to operation in interrupt driven mode. This method is
|
|
|
|
* called when the serial port is opened. Normally, this is just after the
|
|
|
|
* the setup() method is called, however, the serial console may operate in
|
|
|
|
* a non-interrupt driven mode during the boot phase.
|
|
|
|
*
|
|
|
|
* RX and TX interrupts are not enabled when by the attach method (unless the
|
|
|
|
* hardware supports multiple levels of interrupt enabling). The RX and TX
|
|
|
|
* interrupts are not enabled until the txint() and rxint() methods are called.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static int u16550_attach(struct uart_dev_s *dev)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 01:58:10 +01:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Attach and enable the IRQ */
|
|
|
|
|
2017-02-27 17:44:13 +01:00
|
|
|
ret = irq_attach(priv->irq, u16550_interrupt, dev);
|
2011-03-10 01:58:10 +01:00
|
|
|
#ifndef CONFIG_ARCH_NOINTC
|
|
|
|
if (ret == OK)
|
|
|
|
{
|
2012-07-15 16:56:25 +02:00
|
|
|
/* Enable the interrupt (RX and TX interrupts are still disabled
|
|
|
|
* in the UART
|
|
|
|
*/
|
2011-03-10 01:58:10 +01:00
|
|
|
|
2012-07-15 16:56:25 +02:00
|
|
|
up_enable_irq(priv->irq);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
2011-03-10 05:13:44 +01:00
|
|
|
#endif
|
2017-09-30 20:59:33 +02:00
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_detach
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Detach UART interrupts. This method is called when the serial port is
|
|
|
|
* closed normally just before the shutdown method is called. The exception is
|
|
|
|
* the serial console which is never shutdown.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2015-10-04 23:04:00 +02:00
|
|
|
static void u16550_detach(FAR struct uart_dev_s *dev)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2017-02-27 17:44:13 +01:00
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
up_disable_irq(priv->irq);
|
2011-03-10 01:58:10 +01:00
|
|
|
irq_detach(priv->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_interrupt
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is the UART interrupt handler. It will be invoked when an
|
|
|
|
* interrupt received on the 'irq' It should call uart_transmitchars or
|
|
|
|
* uart_receivechar to perform the appropriate data transfers. The
|
|
|
|
* interrupt handling logic must be able to map the 'irq' number into the
|
2011-03-10 05:13:44 +01:00
|
|
|
* appropriate u16550_s structure in order to call these functions.
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-02-27 17:44:13 +01:00
|
|
|
static int u16550_interrupt(int irq, FAR void *context, FAR void *arg)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2017-09-30 20:59:33 +02:00
|
|
|
FAR struct uart_dev_s *dev = (struct uart_dev_s *)arg;
|
|
|
|
FAR struct u16550_s *priv;
|
|
|
|
uint32_t status;
|
|
|
|
int passes;
|
2011-03-10 01:58:10 +01:00
|
|
|
|
2017-02-27 17:44:13 +01:00
|
|
|
DEBUGASSERT(dev != NULL && dev->priv != NULL);
|
2015-10-10 18:41:00 +02:00
|
|
|
priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Loop until there are no characters to be transferred or,
|
|
|
|
* until we have been looping for a long time.
|
|
|
|
*/
|
|
|
|
|
|
|
|
for (passes = 0; passes < 256; passes++)
|
|
|
|
{
|
|
|
|
/* Get the current UART status and check for loop
|
|
|
|
* termination conditions
|
|
|
|
*/
|
|
|
|
|
2012-07-15 16:56:25 +02:00
|
|
|
status = u16550_serialin(priv, UART_IIR_OFFSET);
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* The UART_IIR_INTSTATUS bit should be zero if there are pending
|
|
|
|
* interrupts
|
|
|
|
*/
|
|
|
|
|
|
|
|
if ((status & UART_IIR_INTSTATUS) != 0)
|
|
|
|
{
|
|
|
|
/* Break out of the loop when there is no longer a
|
|
|
|
* pending interrupt
|
|
|
|
*/
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle the interrupt by its interrupt ID field */
|
|
|
|
|
|
|
|
switch (status & UART_IIR_INTID_MASK)
|
|
|
|
{
|
|
|
|
/* Handle incoming, receive bytes (with or without timeout) */
|
|
|
|
|
|
|
|
case UART_IIR_INTID_RDA:
|
|
|
|
case UART_IIR_INTID_CTI:
|
|
|
|
{
|
|
|
|
uart_recvchars(dev);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle outgoing, transmit bytes */
|
|
|
|
|
|
|
|
case UART_IIR_INTID_THRE:
|
|
|
|
{
|
|
|
|
uart_xmitchars(dev);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Just clear modem status interrupts (UART1 only) */
|
|
|
|
|
|
|
|
case UART_IIR_INTID_MSI:
|
|
|
|
{
|
|
|
|
/* Read the modem status register (MSR) to clear */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
status = u16550_serialin(priv, UART_MSR_OFFSET);
|
2017-01-15 20:00:50 +01:00
|
|
|
sinfo("MSR: %02x\n", status);
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Just clear any line status interrupts */
|
|
|
|
|
|
|
|
case UART_IIR_INTID_RLS:
|
|
|
|
{
|
|
|
|
/* Read the line status register (LSR) to clear */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
status = u16550_serialin(priv, UART_LSR_OFFSET);
|
2017-01-15 20:00:50 +01:00
|
|
|
sinfo("LSR: %02x\n", status);
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* There should be no other values */
|
|
|
|
|
|
|
|
default:
|
|
|
|
{
|
2017-09-30 20:59:33 +02:00
|
|
|
serr("ERROR: Unexpected IIR: %02x\n", status);
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-07-15 16:56:25 +02:00
|
|
|
|
|
|
|
return OK;
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_ioctl
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* All ioctl calls will be routed through this method
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static int u16550_ioctl(struct file *filep, int cmd, unsigned long arg)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2017-09-30 20:59:33 +02:00
|
|
|
FAR struct inode *inode = filep->f_inode;
|
|
|
|
FAR struct uart_dev_s *dev = inode->i_private;
|
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2016-07-12 08:50:58 +02:00
|
|
|
int ret;
|
2015-08-03 14:32:51 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
|
2016-07-12 08:50:58 +02:00
|
|
|
ret = uart_ioctl(filep, cmd, arg);
|
2015-08-03 14:32:51 +02:00
|
|
|
|
|
|
|
if (ret != -ENOTTY)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-09-30 20:59:33 +02:00
|
|
|
|
2016-07-12 08:50:58 +02:00
|
|
|
#else
|
|
|
|
ret = OK;
|
2015-08-03 14:32:51 +02:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
2013-04-25 23:52:48 +02:00
|
|
|
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
|
2011-03-10 01:58:10 +01:00
|
|
|
case TIOCSERGSTRUCT:
|
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *user = (FAR struct u16550_s *)arg;
|
2012-07-15 16:56:25 +02:00
|
|
|
if (!user)
|
|
|
|
{
|
2017-09-30 20:59:33 +02:00
|
|
|
ret = -EINVAL;
|
2012-07-15 16:56:25 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
memcpy(user, dev, sizeof(struct u16550_s));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2013-04-25 23:52:48 +02:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
|
|
|
|
{
|
2016-02-14 14:32:58 +01:00
|
|
|
irqstate_t flags = enter_critical_section();
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_enablebreaks(priv, true);
|
2016-02-14 14:32:58 +01:00
|
|
|
leave_critical_section(flags);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
2016-02-14 14:32:58 +01:00
|
|
|
flags = enter_critical_section();
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_enablebreaks(priv, false);
|
2016-02-14 14:32:58 +01:00
|
|
|
leave_critical_section(flags);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2018-08-26 19:30:51 +02:00
|
|
|
#if defined(CONFIG_SERIAL_TERMIOS) && !defined(CONFIG_16550_SUPRESS_CONFIG)
|
|
|
|
case TCGETS:
|
|
|
|
{
|
|
|
|
FAR struct termios *termiosp = (FAR struct termios *)arg;
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
if (!termiosp)
|
|
|
|
{
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
flags = enter_critical_section();
|
|
|
|
|
|
|
|
cfsetispeed(termiosp, priv->baud);
|
|
|
|
termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
|
|
|
|
((priv->parity == 1) ? PARODD : 0);
|
|
|
|
termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0;
|
2018-08-26 19:37:16 +02:00
|
|
|
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
|
|
|
termiosp->c_cflag |= priv->flow ? CRTSCTS : 0;
|
|
|
|
#endif
|
2018-08-26 19:30:51 +02:00
|
|
|
|
|
|
|
switch (priv->bits)
|
|
|
|
{
|
|
|
|
case 5:
|
|
|
|
termiosp->c_cflag |= CS5;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 6:
|
|
|
|
termiosp->c_cflag |= CS6;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 7:
|
|
|
|
termiosp->c_cflag |= CS7;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 8:
|
|
|
|
default:
|
|
|
|
termiosp->c_cflag |= CS8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
leave_critical_section(flags);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TCSETS:
|
|
|
|
{
|
|
|
|
FAR struct termios *termiosp = (FAR struct termios *)arg;
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
if (!termiosp)
|
|
|
|
{
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
flags = enter_critical_section();
|
|
|
|
|
|
|
|
switch (termiosp->c_cflag & CSIZE)
|
|
|
|
{
|
|
|
|
case CS5:
|
|
|
|
priv->bits = 5;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CS6:
|
|
|
|
priv->bits = 6;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CS7:
|
|
|
|
priv->bits = 7;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CS8:
|
|
|
|
default:
|
|
|
|
priv->bits = 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((termiosp->c_cflag & PARENB) != 0)
|
|
|
|
{
|
|
|
|
priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
priv->parity = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->baud = cfgetispeed(termiosp);
|
|
|
|
priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0;
|
2018-08-26 19:37:16 +02:00
|
|
|
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
|
|
|
priv->flow = (termiosp->c_cflag & CRTSCTS) != 0;
|
|
|
|
#endif
|
2018-08-26 19:30:51 +02:00
|
|
|
|
|
|
|
u16550_setup(dev);
|
|
|
|
leave_critical_section(flags);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
default:
|
2017-09-30 20:59:33 +02:00
|
|
|
ret = -ENOTTY;
|
2011-03-10 01:58:10 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_receive
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Called (usually) from the interrupt level to receive one
|
|
|
|
* character from the UART. Error bits associated with the
|
|
|
|
* receipt are provided in the return 'status'.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static int u16550_receive(struct uart_dev_s *dev, uint32_t *status)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 01:58:10 +01:00
|
|
|
uint32_t rbr;
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
*status = u16550_serialin(priv, UART_LSR_OFFSET);
|
|
|
|
rbr = u16550_serialin(priv, UART_RBR_OFFSET);
|
2011-03-10 01:58:10 +01:00
|
|
|
return rbr;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_rxint
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable RX interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static void u16550_rxint(struct uart_dev_s *dev, bool enable)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2017-09-30 20:59:33 +02:00
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
priv->ier |= UART_IER_ERBFI;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
priv->ier &= ~UART_IER_ERBFI;
|
|
|
|
}
|
2017-02-27 17:44:13 +01:00
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_IER_OFFSET, priv->ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_rxavailable
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the receive fifo is not empty
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static bool u16550_rxavailable(struct uart_dev_s *dev)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 05:13:44 +01:00
|
|
|
return ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_DR) != 0);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
2018-08-26 19:20:15 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: u16550_dma*
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Stubbed out DMA-related methods
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2018-08-26 19:37:16 +02:00
|
|
|
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
|
|
|
static bool u16550_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
|
|
|
|
bool upper)
|
|
|
|
{
|
|
|
|
#ifndef CONFIG_16550_SUPRESS_CONFIG
|
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
|
|
|
|
|
|
|
if (priv->flow)
|
|
|
|
{
|
|
|
|
/* Disable Rx interrupt to prevent more data being from
|
|
|
|
* peripheral if the RX buffer is near full. When hardware
|
|
|
|
* RTS is enabled, this will prevent more data from coming
|
|
|
|
* in. Otherwise, enable Rx interrupt to make sure that more
|
|
|
|
* input is received.
|
|
|
|
*/
|
|
|
|
|
|
|
|
u16550_rxint(dev, !upper);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-08-26 21:14:26 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: u16550_dma*
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Stub functions used when serial DMA is enabled.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2018-08-26 19:20:15 +02:00
|
|
|
#ifdef CONFIG_SERIAL_DMA
|
|
|
|
static void u16550_dmasend(FAR struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void u16550_dmareceive(FAR struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void u16550_dmarxfree(FAR struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void u16550_dmatxavail(FAR struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-03-10 01:58:10 +01:00
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_send
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This method will send one byte on the UART
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static void u16550_send(struct uart_dev_s *dev, int ch)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_txint
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable TX interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static void u16550_txint(struct uart_dev_s *dev, bool enable)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 01:58:10 +01:00
|
|
|
irqstate_t flags;
|
|
|
|
|
2016-02-14 14:32:58 +01:00
|
|
|
flags = enter_critical_section();
|
2011-03-10 01:58:10 +01:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
priv->ier |= UART_IER_ETBEI;
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_IER_OFFSET, priv->ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Fake a TX interrupt here by just calling uart_xmitchars() with
|
|
|
|
* interrupts disabled (note this may recurse).
|
|
|
|
*/
|
|
|
|
|
|
|
|
uart_xmitchars(dev);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
priv->ier &= ~UART_IER_ETBEI;
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_IER_OFFSET, priv->ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
2012-07-15 16:56:25 +02:00
|
|
|
|
2016-02-14 14:32:58 +01:00
|
|
|
leave_critical_section(flags);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_txready
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the tranmsit fifo is not full
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static bool u16550_txready(struct uart_dev_s *dev)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2011-03-10 05:13:44 +01:00
|
|
|
return ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: u16550_txempty
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Return true if the transmit fifo is empty
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
static bool u16550_txempty(struct uart_dev_s *dev)
|
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv;
|
2018-08-26 19:17:33 +02:00
|
|
|
return ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_TEMT) != 0);
|
2011-03-10 05:13:44 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: u16550_putc
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Write one character to the UART (polled)
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2018-08-26 19:28:57 +02:00
|
|
|
#ifdef HAVE_16550_CONSOLE
|
2015-10-10 18:41:00 +02:00
|
|
|
static void u16550_putc(FAR struct u16550_s *priv, int ch)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-08-03 11:42:39 +02:00
|
|
|
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
2018-08-26 19:28:57 +02:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/****************************************************************************
|
2018-08-26 19:28:57 +02:00
|
|
|
* Public Functions
|
2011-03-10 01:58:10 +01:00
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: up_earlyserialinit
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Performs the low level UART initialization early in debug so that the
|
|
|
|
* serial console will be available during bootup. This must be called
|
|
|
|
* before uart_serialinit.
|
|
|
|
*
|
|
|
|
* NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup()
|
|
|
|
* very early in the boot sequence.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
void up_earlyserialinit(void)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
|
|
|
/* Configuration whichever one is the console */
|
|
|
|
|
|
|
|
#ifdef CONSOLE_DEV
|
|
|
|
CONSOLE_DEV.isconsole = true;
|
2018-08-26 19:37:16 +02:00
|
|
|
#ifndef CONFIG_16550_SUPRESS_INITIAL_CONFIG
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_setup(&CONSOLE_DEV);
|
2011-03-10 01:58:10 +01:00
|
|
|
#endif
|
2018-08-26 19:37:16 +02:00
|
|
|
#endif
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: up_serialinit
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Register serial console and serial ports. This assumes that
|
2011-03-10 05:13:44 +01:00
|
|
|
* up_earlyserialinit was called previously.
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
void up_serialinit(void)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
|
|
|
#ifdef CONSOLE_DEV
|
|
|
|
(void)uart_register("/dev/console", &CONSOLE_DEV);
|
|
|
|
#endif
|
|
|
|
#ifdef TTYS0_DEV
|
|
|
|
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
|
|
|
|
#endif
|
|
|
|
#ifdef TTYS1_DEV
|
|
|
|
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
|
|
|
|
#endif
|
|
|
|
#ifdef TTYS2_DEV
|
|
|
|
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
|
|
|
|
#endif
|
|
|
|
#ifdef TTYS3_DEV
|
|
|
|
(void)uart_register("/dev/ttyS3", &TTYS3_DEV);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2011-03-10 05:13:44 +01:00
|
|
|
* Name: up_putc
|
2011-03-10 01:58:10 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Provide priority, low-level access to support OS debug writes
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef HAVE_16550_CONSOLE
|
2011-03-10 05:13:44 +01:00
|
|
|
int up_putc(int ch)
|
2011-03-10 01:58:10 +01:00
|
|
|
{
|
2015-10-10 18:41:00 +02:00
|
|
|
FAR struct u16550_s *priv = (FAR struct u16550_s *)CONSOLE_DEV.priv;
|
2011-03-10 01:58:10 +01:00
|
|
|
uart_datawidth_t ier;
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_disableuartint(priv, &ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
|
|
|
|
/* Check for LF */
|
|
|
|
|
|
|
|
if (ch == '\n')
|
|
|
|
{
|
|
|
|
/* Add CR */
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_putc(priv, '\r');
|
2011-03-10 01:58:10 +01:00
|
|
|
}
|
|
|
|
|
2011-03-10 05:13:44 +01:00
|
|
|
u16550_putc(priv, ch);
|
|
|
|
u16550_restoreuartint(priv, ier);
|
2011-03-10 01:58:10 +01:00
|
|
|
return ch;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-09-05 19:20:19 +02:00
|
|
|
#endif /* CONFIG_16550_UART */
|