nuttx/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script

/****************************************************************************
 * boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/

/* The STM32LO72CZ has 192Kb of FLASH beginning at address 0x0800:0000.
 * 20Kb of SRAM and 6Kb of EEPROM
 *
 * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
 * where the code expects to begin execution by jumping to the entry point in
 * the 0x0800:0000 address range.
 */

MEMORY
{
    flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K
    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
}

OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
        .text : {
                _stext = ABSOLUTE(.);
                *(.vectors)
                *(.text .text.*)
                *(.fixup)
                *(.gnu.warning)
                *(.rodata .rodata.*)
                *(.gnu.linkonce.t.*)
                *(.glue_7)
                *(.glue_7t)
                *(.got)
                *(.gcc_except_table)
                *(.gnu.linkonce.r.*)
                _etext = ABSOLUTE(.);
        } > flash

        .init_section : ALIGN(4) {
                _sinit = ABSOLUTE(.);
                *(.init_array .init_array.*)
                _einit = ABSOLUTE(.);
        } > flash

        .ARM.extab : ALIGN(4) {
                *(.ARM.extab*)
        } > flash

        .ARM.exidx : ALIGN(4) {
                __exidx_start = ABSOLUTE(.);
                *(.ARM.exidx*)
                __exidx_end = ABSOLUTE(.);
        } > flash

        _eronly = ABSOLUTE(.);

        /* The RAM vector table (if present) should lie at the beginning of SRAM */

        .ram_vectors : {
                *(.ram_vectors)
        } > sram

        .data : ALIGN(4) {
                _sdata = ABSOLUTE(.);
                *(.data .data.*)
                *(.gnu.linkonce.d.*)
                CONSTRUCTORS
                _edata = ABSOLUTE(.);
        } > sram AT > flash

        .bss : ALIGN(4) {
                _sbss = ABSOLUTE(.);
                *(.bss .bss.*)
                *(.gnu.linkonce.b.*)
                *(COMMON)
                _ebss = ABSOLUTE(.);
        } > sram

        /* Stabs debugging sections. */
        .stab 0 : { *(.stab) }
        .stabstr 0 : { *(.stabstr) }
        .stab.excl 0 : { *(.stab.excl) }
        .stab.exclstr 0 : { *(.stab.exclstr) }
        .stab.index 0 : { *(.stab.index) }
        .stab.indexstr 0 : { *(.stab.indexstr) }
        .comment 0 : { *(.comment) }
        .debug_abbrev 0 : { *(.debug_abbrev) }
        .debug_info 0 : { *(.debug_info) }
        .debug_line 0 : { *(.debug_line) }
        .debug_pubnames 0 : { *(.debug_pubnames) }
        .debug_aranges 0 : { *(.debug_aranges) }
}