2022-06-09 22:34:30 +02:00
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/****************************************************************************
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2022-10-31 22:43:58 +01:00
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* boards/xtensa/esp32s3/common/scripts/esp32s3_memory.ld
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2022-06-09 22:34:30 +02:00
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* ESP32-S3 Linker Script Memory Layout
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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2022-10-31 22:43:58 +01:00
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* esp32s3_sections.ld contains output sections to link compiler output
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2022-06-09 22:34:30 +02:00
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* into these memory blocks.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#define SRAM_IRAM_START 0x40370000
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#define SRAM_DIRAM_I_START 0x40378000
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#define SRAM_IRAM_END 0x403ba000
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#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
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#define SRAM_DRAM_START 0x3fc88000
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/* 2nd stage bootloader iram_loader_seg start address */
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#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
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#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
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#define ICACHE_SIZE 0x8000
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#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define DCACHE_SIZE 0x10000
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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#ifdef CONFIG_ESP32S3_FLASH_4M
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# define FLASH_SIZE 0x400000
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#elif defined (CONFIG_ESP32S3_FLASH_8M)
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# define FLASH_SIZE 0x800000
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#elif defined (CONFIG_ESP32S3_FLASH_16M)
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# define FLASH_SIZE 0x1000000
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#endif
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MEMORY
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{
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/* Below values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and eg allow bytewise access.
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*/
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/* IRAM for CPU */
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iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE
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/* Flash mapped instruction data. */
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/* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20
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/* Shared data RAM, excluding memory reserved for bootloader and ROM
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* bss/data/stack.
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*/
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dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE
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/* Flash mapped constant data */
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/* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000
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/* RTC fast memory (same block as above), viewed from data bus */
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rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data,
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* if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
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}
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#ifdef CONFIG_ESP32S3_RUN_IRAM
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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REGION_ALIAS("default_code_seg", irom0_0_seg);
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#endif /* CONFIG_ESP32S3_RUN_IRAM */
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