2011-11-22 01:10:56 +01:00
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/************************************************************************************
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* arch/arm/include/stm32s/stm32f10xxx_irq.h
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*
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2012-07-19 20:02:32 +02:00
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* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
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2011-11-22 01:10:56 +01:00
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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*/
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2015-07-21 19:30:45 +02:00
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#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H
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2011-11-22 01:10:56 +01:00
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/************************************************************************************
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2015-04-08 16:04:12 +02:00
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* Pre-processor Definitions
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2011-11-22 01:10:56 +01:00
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************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32/irq.h
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*
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* External interrupts (vectors >= 16)
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*/
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2012-11-02 14:46:45 +01:00
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/* Value line devices */
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2012-11-08 19:05:39 +01:00
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2012-11-02 14:46:45 +01:00
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#if defined(CONFIG_STM32_VALUELINE)
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
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# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
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# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
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# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
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# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
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# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
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# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
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# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
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# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
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# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
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# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
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# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
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# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
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# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
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2012-07-19 20:02:32 +02:00
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# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
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# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */
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2012-11-08 19:05:39 +01:00
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# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */
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# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */
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# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */
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# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */
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2012-07-19 20:02:32 +02:00
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# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
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# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */
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# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
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# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */
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# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
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# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */
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2012-07-19 20:02:32 +02:00
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# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
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# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
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# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
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# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
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# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
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# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
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# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
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# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
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# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
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# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
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# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
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# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
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# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
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# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */
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2012-07-19 20:02:32 +02:00
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# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
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# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
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# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
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2012-11-08 19:05:39 +01:00
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# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */
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# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
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2012-11-08 19:05:39 +01:00
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# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
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# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
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# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
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2016-05-25 20:31:32 +02:00
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# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
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2012-07-19 20:02:32 +02:00
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# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
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# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
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# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
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# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
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# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
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2012-11-02 14:46:45 +01:00
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# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
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# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
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2013-12-23 18:13:56 +01:00
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# define NR_VECTORS (77)
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2012-11-02 14:46:45 +01:00
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# define NR_IRQS (77)
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/* Connectivity Line Devices */
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2012-07-19 20:02:32 +02:00
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#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
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# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
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# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
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# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
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# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
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# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
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# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
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# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
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# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
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# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
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# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
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# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
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# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
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# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
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# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
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# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
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# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
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# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
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# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
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# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */
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# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */
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# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */
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# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */
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# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
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# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
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# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
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# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
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# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
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# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
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# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
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# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
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# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
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# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
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# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
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# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
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# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
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# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
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# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
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# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
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# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
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# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
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2012-07-19 16:33:14 +02:00
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# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_OTGFSWKUP (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
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2012-08-10 19:07:02 +02:00
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# define STM32_IRQ_RESERVED0 (59) /* 43: Reserved 0 */
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# define STM32_IRQ_RESERVED1 (60) /* 44: Reserved 1 */
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# define STM32_IRQ_RESERVED2 (61) /* 45: Reserved 2 */
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# define STM32_IRQ_RESERVED3 (62) /* 46: Reserved 3 */
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# define STM32_IRQ_RESERVED4 (63) /* 47: Reserved 4 */
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# define STM32_IRQ_RESERVED5 (64) /* 48: Reserved 5 */
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# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
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# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
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# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */
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# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
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# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
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# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
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# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
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# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
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# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
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# define STM32_IRQ_DMA2CH4 (75) /* 59: DMA2 Channel 4 global interrupt */
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# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
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# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */
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# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
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# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */
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2016-06-10 19:52:58 +02:00
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# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */
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# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
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# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
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2013-12-23 18:13:56 +01:00
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# define NR_VECTORS (84)
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2011-11-22 01:10:56 +01:00
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# define NR_IRQS (84)
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2012-11-02 14:46:45 +01:00
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/* Medium and High Density Devices */
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2011-11-22 01:10:56 +01:00
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#else
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# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
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# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
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# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
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# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
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# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
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# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
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# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
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# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
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# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
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# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
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# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
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# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
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# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
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# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
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# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
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# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
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# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
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# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
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# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
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# define STM32_IRQ_USBHPCANTX (35) /* 19: USB High Priority or CAN TX interrupts*/
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# define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/
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# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */
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# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */
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# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
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# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
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# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
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# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
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# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
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# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
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# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
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# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
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# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
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# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
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# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
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# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
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# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
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# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
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# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
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# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
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# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
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# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
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2012-07-19 16:33:14 +02:00
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# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */
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2011-11-22 01:10:56 +01:00
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# define STM32_IRQ_USBWKUP (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/
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# define STM32_IRQ_TIM8BRK (59) /* 43: TIM8 Break interrupt */
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# define STM32_IRQ_TIM8UP (60) /* 44: TIM8 Update interrupt */
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# define STM32_IRQ_TIM8TRGCOM (61) /* 45: TIM8 Trigger and Commutation interrupts */
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# define STM32_IRQ_TIM8CC (62) /* 46: TIM8 Capture Compare interrupt */
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# define STM32_IRQ_ADC3 (63) /* 47: ADC3 global interrupt */
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# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
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# define STM32_IRQ_SDIO (65) /* 49: SDIO global interrupt */
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# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
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# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
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# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */
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# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
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# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
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# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
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# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
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# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
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# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
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# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */
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2013-12-23 18:13:56 +01:00
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# define NR_VECTORS (76)
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2011-11-22 01:10:56 +01:00
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# define NR_IRQS (76)
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2013-02-07 00:09:09 +01:00
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/* Convenience definitions for interrupts with multiple functions */
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# define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX
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# define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX
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# define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0
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# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0
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2011-11-22 01:10:56 +01:00
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
|
2015-06-13 03:26:01 +02:00
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extern "C"
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{
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2011-11-22 01:10:56 +01:00
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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2015-07-21 19:30:45 +02:00
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#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H */
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2011-11-22 01:10:56 +01:00
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