152 lines
4.1 KiB
Plaintext
152 lines
4.1 KiB
Plaintext
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/****************************************************************************
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* boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED
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MEMORY
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{
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
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dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
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sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
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sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
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sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
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sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
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sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
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bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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}
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#else
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MEMORY
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{
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE
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dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
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sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
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/* shared memory on SRAM3 */
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shmem (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
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sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
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bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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}
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#endif
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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ENTRY(_stext)
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SECTIONS
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{
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.text :
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{
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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.init_section :
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{
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_sinit = ABSOLUTE(.);
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*(.init_array .init_array.*)
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_einit = ABSOLUTE(.);
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} > flash
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.ARM.extab :
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{
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*(.ARM.extab*)
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} > flash
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__exidx_start = ABSOLUTE(.);
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.ARM.exidx :
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{
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*(.ARM.exidx*)
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} > flash
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__exidx_end = ABSOLUTE(.);
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_eronly = ABSOLUTE(.);
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.bss :
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{
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > sram
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.shmem :
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{
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. = ALIGN(4);
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*(.shmem);
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KEEP(*(.shmem))
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} > shmem
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/* Emit the the D3 power domain section for locating BDMA data
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*
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* Static data with locate_data(".sram4") will be located
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* at start of SRAM4; the rest of SRAM4 will be added to the heap.
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*/
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.sram4_reserve (NOLOAD) :
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{
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*(.sram4)
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. = ALIGN(4);
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_sram4_heap_start = ABSOLUTE(.);
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} > sram4
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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}
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