2020-12-02 23:54:34 +01:00
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/****************************************************************************
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* boards/arm/imxrt/teensy-4.x/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_IMXRT_TEENSY_4_INCLUDE_BOARD_H
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#define __BOARDS_ARM_IMXRT_TEENSY_4_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/* Do not include i.MXRT header files here. */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Set VDD_SOC to 1.25V */
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#define IMXRT_VDD_SOC (0x12)
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/* Set Arm PLL (PLL1) to fOut = (24Mhz * ARM_PLL_DIV_SELECT/2) /
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* ARM_PODF_DIVISOR
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* 600Mhz = (24Mhz * ARM_PLL_DIV_SELECT/2) /
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* ARM_PODF_DIVISOR
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* ARM_PLL_DIV_SELECT = 100
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* ARM_PODF_DIVISOR = 2
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* 600Mhz = (24Mhz * 100/2) / 2
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*
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* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
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* 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER
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* IMXRT_ARM_CLOCK_DIVIDER = 1
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* 600Mhz = 600Mhz / 1
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*
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* PRE_PERIPH_CLK_SEL = PRE_PERIPH_CLK_SEL_PLL1
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* PERIPH_CLK_SEL = 1 (0 select PERIPH_CLK2_PODF,
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* 1 select PRE_PERIPH_CLK_SEL_PLL1)
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* PERIPH_CLK = 600Mhz
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*
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* IPG_CLOCK_ROOT = AHB_CLOCK_ROOT / IMXRT_IPG_PODF_DIVIDER
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* IMXRT_IPG_PODF_DIVIDER = 4
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* 150Mhz = 600Mhz / 4
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*
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* PRECLK_CLOCK_ROOT = IPG_CLOCK_ROOT /
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* IMXRT_PERCLK_PODF_DIVIDER
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* IMXRT_PERCLK_PODF_DIVIDER = 9
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* 16.6Mhz = 150Mhz / 9
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*
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* SEMC_CLK_ROOT = 600Mhz / IMXRT_SEMC_PODF_DIVIDER
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* (labeled AIX_PODF in 18.2)
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* IMXRT_SEMC_PODF_DIVIDER = 8
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* 75Mhz = 600Mhz / 8
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*
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* Set Sys PLL (PLL2) to fOut = (24Mhz * (20+(2*(DIV_SELECT)))
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* 528Mhz = (24Mhz * (20+(2*(1)))
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*
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* Set USB1 PLL (PLL3) to fOut = (24Mhz * 20)
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* 480Mhz = (24Mhz * 20)
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*
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* Set LPSPI PLL3 PFD0 to fOut = (480Mhz / 12 * 18)
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* 720Mhz = (480Mhz / 12 * 18)
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* 90Mhz = (720Mhz / LSPI_PODF_DIVIDER)
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*
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* Set LPI2C PLL3 / 8 to fOut = (480Mhz / 8)
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* 60Mhz = (480Mhz / 8)
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* 12Mhz = (60Mhz / LSPI_PODF_DIVIDER)
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*
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* These clock frequencies can be verified via the CCM_CLKO1 pin and sending
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* the appropriate clock to it with something like;
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*
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* putreg32( <Clk number> | CCM_CCOSR_CLKO1_EN , IMXRT_CCM_CCOSR);
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* imxrt_config_gpio(GPIO_CCM_CLKO1);
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*/
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#define BOARD_XTAL_FREQUENCY 24000000
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#define IMXRT_PRE_PERIPH_CLK_SEL CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1
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#define IMXRT_PERIPH_CLK_SEL CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH
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#define IMXRT_ARM_PLL_DIV_SELECT 100
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#define IMXRT_ARM_PODF_DIVIDER 2
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#define IMXRT_AHB_PODF_DIVIDER 1
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#define IMXRT_IPG_PODF_DIVIDER 4
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#define IMXRT_PERCLK_CLK_SEL CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT
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#define IMXRT_PERCLK_PODF_DIVIDER 9
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#define IMXRT_SEMC_PODF_DIVIDER 8
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#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0
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#define IMXRT_LSPI_PODF_DIVIDER 8
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#define IMXRT_LPI2C_CLK_SELECT CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M
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#define IMXRT_LSI2C_PODF_DIVIDER 5
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#define IMXRT_CAN_CLK_SELECT CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80
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#define IMXRT_CAN_PODF_DIVIDER 1
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#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22
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#define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20
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#define BOARD_CPU_FREQUENCY \
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(BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER
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/* Define this to enable tracing */
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#if 0
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# define IMXRT_TRACE_PODF_DIVIDER 1
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# define IMXRT_TRACE_CLK_SELECT CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0
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#endif
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/* LED definitions **********************************************************/
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2020-12-03 18:38:39 +01:00
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/* There are two LED status indicators located on the Teensy 4.x board.
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2020-12-02 23:54:34 +01:00
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* The functions of these LEDs include:
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*
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2020-12-03 18:38:39 +01:00
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* - RED LED (loading status)
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* - dim: ready
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* - bright: writing
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* - blink: no USB
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* - USER LED (D3)
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2020-12-02 23:54:34 +01:00
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*
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2020-12-03 18:38:39 +01:00
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* Only a single LED, D3, is under software control.
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2020-12-02 23:54:34 +01:00
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_USERLED 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_USERLED_BIT (1 << BOARD_USERLED)
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/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/imxrt_autoleds.c. The LED is used to encode
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* OS-related events as follows:
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*
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* -------------------- ----------------------------- ------
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* SYMBOL Meaning LED
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* -------------------- ----------------------------- ------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON */
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#define LED_INIRQ 2 /* In an interrupt N/C */
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#define LED_SIGNAL 2 /* In a signal handler N/C */
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#define LED_ASSERTION 2 /* An assertion failed N/C */
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#define LED_PANIC 3 /* The system has crashed FLASH */
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#undef LED_IDLE /* Not used */
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/* Thus if the LED is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If the LED is flashing at approximately
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* 2Hz, then a fatal error has been detected and the system has halted.
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*/
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/* SDIO *********************************************************************/
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/* Pin drive characteristics - drive strength in particular may need tuning
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* for specific boards, but has been checked by scope on the EVKB to make
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* sure shapes are square with minimal ringing.
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*/
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#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | IOMUX_USDHC1_DATAX_DEFAULT)
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#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | IOMUX_USDHC1_DATAX_DEFAULT)
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#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT)
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#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA2_1 | IOMUX_USDHC1_DATAX_DEFAULT)
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#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT)
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#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT)
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#define PIN_USDHC1_CD (PIN_USDHC1_D3)
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/* 386 KHz for initial inquiry stuff */
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#define BOARD_USDHC_IDMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV256
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#define BOARD_USDHC_IDMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(2)
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/* 24.8MHz for other modes */
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#define BOARD_USDHC_MMCMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8
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#define BOARD_USDHC_MMCMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1)
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#define BOARD_USDHC_SD1MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8
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#define BOARD_USDHC_SD1MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1)
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#define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8
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#define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1)
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/* ETH Disambiguation *******************************************************/
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#define GPIO_ENET_TX_DATA00 (GPIO_ENET_TX_DATA00_1| \
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IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_07 */
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#define GPIO_ENET_TX_DATA01 (GPIO_ENET_TX_DATA01_1| \
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IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_08 */
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#define GPIO_ENET_RX_DATA00 (GPIO_ENET_RX_DATA00_1| \
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IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_04 */
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#define GPIO_ENET_RX_DATA01 (GPIO_ENET_RX_DATA01_1| \
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IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_05 */
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#define GPIO_ENET_MDIO (GPIO_ENET_MDIO_1|IOMUX_ENET_MDIO_DEFAULT) /* GPIO_B1_15 */
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#define GPIO_ENET_MDC (GPIO_ENET_MDC_1|IOMUX_ENET_MDC_DEFAULT) /* GPIO_B1_14 */
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#define GPIO_ENET_RX_EN (GPIO_ENET_RX_EN_1|IOMUX_ENET_EN_DEFAULT) /* GPIO_B1_06 */
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#define GPIO_ENET_RX_ER (GPIO_ENET_RX_ER_1|IOMUX_ENET_RXERR_DEFAULT) /* GPIO_B1_11 */
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#define GPIO_ENET_TX_CLK (GPIO_ENET_REF_CLK_2|\
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IOMUX_ENET_TX_CLK_DEFAULT) /* GPIO_B1_10 */
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#define GPIO_ENET_TX_EN (GPIO_ENET_TX_EN_1|IOMUX_ENET_EN_DEFAULT) /* GPIO_B1_09 */
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/* PIO Disambiguation *******************************************************/
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2020-12-03 18:38:39 +01:00
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/* LPUARTs */
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#define GPIO_LPUART1_RX (GPIO_LPUART1_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B0_13 */
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#define GPIO_LPUART1_TX (GPIO_LPUART1_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B0_12 */
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_07 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_06 */
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#define GPIO_LPUART6_RX (GPIO_LPUART6_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B0_03 */
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#define GPIO_LPUART6_TX (GPIO_LPUART6_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B0_02 */
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/* LPI2Cs */
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#define GPIO_LPI2C1_SDA (GPIO_LPI2C1_SDA_2|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B1_01 */
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#define GPIO_LPI2C1_SCL (GPIO_LPI2C1_SCL_2|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B1_00 */
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#define GPIO_LPI2C3_SDA (GPIO_LPI2C3_SDA_1|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B1_06 */
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#define GPIO_LPI2C3_SCL (GPIO_LPI2C3_SCL_1|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B1_07 */
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#define GPIO_LPI2C4_SDA (GPIO_LPI2C4_SDA_1|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B0_13 */
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#define GPIO_LPI2C4_SCL (GPIO_LPI2C4_SCL_1|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B0_12 */
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/* LPSPI3
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*
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* pin 39 GPIO_AD_B1_13 LPSPI3_SDI
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* pin 26 GPIO_AD_B1_14 LPSPI3_SDO
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* pin 27 GPIO_AD_B1_15 LPSPI3_SCK
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*/
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#define GPIO_LPSPI3_MOSI (GPIO_LPSPI3_SDI_1|IOMUX_LPSPI_DEFAULT) /* GPIO_AD_B1_13 */
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#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDO_1|IOMUX_LPSPI_DEFAULT) /* GPIO_AD_B1_14 */
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#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_1|IOMUX_LPSPI_DEFAULT) /* GPIO_AD_B1_15 */
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/* LPSPI4
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*
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* pin 12 GPIO_B0_01 LPSPI3_SDI
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* pin 11 GPIO_B0_02 LPSPI3_SDO
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* pin 13 GPIO_B0_03 LPSPI3_SCK
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*/
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#define GPIO_LPSPI4_MOSI (GPIO_LPSPI4_SDI_2|IOMUX_LPSPI_DEFAULT) /* GPIO_B0_01 */
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#define GPIO_LPSPI4_MISO (GPIO_LPSPI4_SDO_2|IOMUX_LPSPI_DEFAULT) /* GPIO_B0_02 */
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#define GPIO_LPSPI4_SCK (GPIO_LPSPI4_SCK_2|IOMUX_LPSPI_DEFAULT) /* GPIO_B0_03 */
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/* FlexCAN */
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#define GPIO_FLEXCAN1_TX (GPIO_FLEXCAN1_TX_1|IOMUX_CAN_DEFAULT) /* GPIO_AD_B1_08 */
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#define GPIO_FLEXCAN1_RX (GPIO_FLEXCAN1_RX_1|IOMUX_CAN_DEFAULT) /* GPIO_AD_B1_09 */
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#define GPIO_FLEXCAN2_TX (GPIO_FLEXCAN2_TX_1|IOMUX_CAN_DEFAULT) /* GPIO_AD_B0_02 */
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#define GPIO_FLEXCAN2_RX (GPIO_FLEXCAN2_RX_1|IOMUX_CAN_DEFAULT) /* GPIO_AD_B0_03 */
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#define GPIO_FLEXCAN3_TX (GPIO_FLEXCAN3_TX_3|IOMUX_CAN_DEFAULT) /* GPIO_EMC_36 */
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#define GPIO_FLEXCAN3_RX (GPIO_FLEXCAN3_RX_3|IOMUX_CAN_DEFAULT) /* GPIO_EMC_37 */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_IMXRT_TEENSY_4_INCLUDE_BOARD_H */
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