2019-08-19 17:16:08 +02:00
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/****************************************************************************
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* boards/arm/stm32/olimex-stm32-p407/include/board.h
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2016-12-21 00:49:46 +01:00
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*
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2021-03-19 12:39:00 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-12-21 00:49:46 +01:00
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*
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2021-03-19 12:39:00 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-12-21 00:49:46 +01:00
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*
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2021-03-19 12:39:00 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-12-21 00:49:46 +01:00
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*
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2016-12-21 00:49:46 +01:00
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2019-08-19 17:16:08 +02:00
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#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H
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2020-01-31 19:07:39 +01:00
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#define __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H
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2016-12-21 00:49:46 +01:00
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2019-08-19 17:16:08 +02:00
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/****************************************************************************
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2016-12-21 00:49:46 +01:00
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* Included Files
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2016-12-21 00:49:46 +01:00
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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2019-08-19 17:16:08 +02:00
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/****************************************************************************
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2016-12-21 00:49:46 +01:00
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* Pre-processor Definitions
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2016-12-21 00:49:46 +01:00
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2020-05-12 22:36:48 +02:00
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/* Clocking *****************************************************************/
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2016-12-21 00:49:46 +01:00
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC (30-60KHz, uncalibrated)
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* HSE - On-board crystal frequency is 25MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 25000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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2016-12-21 17:45:36 +01:00
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* = (25,000,000 / 25) * 336
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* = 336,000,000
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2016-12-21 00:49:46 +01:00
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* SYSCLK = PLL_VCO / PLLP
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2016-12-21 17:45:36 +01:00
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* = 336,000,000 / 2 = 168,000,000
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2016-12-21 00:49:46 +01:00
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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2016-12-21 17:45:36 +01:00
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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2016-12-21 00:49:46 +01:00
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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2016-12-21 17:45:36 +01:00
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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2016-12-21 00:49:46 +01:00
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2016-12-21 17:45:36 +01:00
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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2016-12-21 00:49:46 +01:00
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2016-12-21 17:45:36 +01:00
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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2016-12-21 00:49:46 +01:00
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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2016-12-21 17:45:36 +01:00
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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2016-12-21 00:49:46 +01:00
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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2016-12-21 17:45:36 +01:00
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/* Timers driven from APB1 will be twice PCLK1 */
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2016-12-21 00:49:46 +01:00
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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2016-12-21 17:45:36 +01:00
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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2016-12-21 00:49:46 +01:00
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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2016-12-21 17:45:36 +01:00
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/* Timers driven from APB2 will be twice PCLK2 */
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2016-12-21 00:49:46 +01:00
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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2016-12-21 17:45:36 +01:00
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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2020-05-12 22:36:48 +02:00
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/* LED definitions **********************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way. The following definitions are used to access individual LEDs.
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2016-12-21 00:49:46 +01:00
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_LED4 3
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#define BOARD_NLEDS 4
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#define BOARD_LED_GREEN1 BOARD_LED1
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#define BOARD_LED_YELLOW BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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#define BOARD_LED_GREEN2 BOARD_LED4
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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#define BOARD_LED4_BIT (1 << BOARD_LED4)
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2020-05-12 22:36:48 +02:00
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on
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* board the Olimex STM32-P407. The following definitions describe how
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* NuttX controls the LEDs:
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2016-12-21 00:49:46 +01:00
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*/
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#define LED_STARTED 0 /* LED1 */
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#define LED_HEAPALLOCATE 1 /* LED2 */
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#define LED_IRQSENABLED 2 /* LED1 + LED2 */
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#define LED_STACKCREATED 3 /* LED3 */
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#define LED_INIRQ 4 /* LED1 + LED3 */
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#define LED_SIGNAL 5 /* LED2 + LED3 */
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
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2020-05-12 22:36:48 +02:00
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/* Button definitions *******************************************************/
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2016-12-21 00:49:46 +01:00
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/* The Olimex STM32-P407 supports seven buttons: */
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2020-06-10 23:31:33 +02:00
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#define BUTTON_TAMPER 0
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#define BUTTON_WKUP 1
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2021-04-08 11:24:25 +02:00
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#ifdef CONFIG_INPUT_DJOYSTICK
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2020-06-10 23:31:33 +02:00
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# define NUM_BUTTONS 2
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#else
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# define JOYSTICK_RIGHT 2
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# define JOYSTICK_UP 3
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# define JOYSTICK_LEFT 4
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# define JOYSTICK_DOWN 5
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# define JOYSTICK_CENTER 6
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# define NUM_BUTTONS 7
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#endif
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#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER)
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#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP)
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2021-04-08 11:24:25 +02:00
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#ifndef CONFIG_INPUT_DJOYSTICK
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2020-06-10 23:31:33 +02:00
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# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT)
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# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP)
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# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT)
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# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN)
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# define JOYSTICK_CENTER_BIT (1 << JOYSTICK_CENTER)
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#endif
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2016-12-21 00:49:46 +01:00
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2020-05-12 22:36:48 +02:00
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/* Alternate function pin selections ****************************************/
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2016-12-21 00:49:46 +01:00
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2016-12-21 18:38:45 +01:00
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/* USART3: */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
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2020-07-02 01:25:39 +02:00
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/* UEXT USART3: This will redefine the above macros if enabled. */
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#ifdef CONFIG_STM32_OLIMEXP407_UEXT_USART3
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# undef GPIO_USART3_RX GPIO_USART3_RX_3
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# undef GPIO_USART3_TX GPIO_USART3_TX_3
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# undef GPIO_USART3_CTS GPIO_USART3_CTS_2
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# undef GPIO_USART3_RTS GPIO_USART3_RTS_2
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# define GPIO_USART3_RX GPIO_USART3_RX_2 /* PC11 */
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# define GPIO_USART3_TX GPIO_USART3_TX_2 /* PC10 */
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#endif
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2017-02-23 20:27:36 +01:00
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/* USART6: */
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#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
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#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
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2016-12-21 18:38:45 +01:00
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/* CAN: */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */
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2017-01-28 17:17:10 +01:00
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/* microSD Connector:
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*
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* ----------------- ----------------- ------------------------
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* SD/MMC CONNECTOR BOARD GPIO CONFIGURATION(s
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* PIN SIGNAL SIGNAL (no remapping)
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* --- ------------- ----------------- -------------------------
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* 1 DAT2/RES SD_D2/USART3_TX/ PC10 GPIO_SDIO_D2
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* SPI3_SCK
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* 2 CD/DAT3/CS SD_D3/USART3_RX/ PC11 GPIO_SDIO_D3
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* SPI3_MISO
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* 3 CMD/DI SD_CMD PD2 GPIO_SDIO_CMD
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* 4 VDD N/A N/A
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* 5 CLK/SCLK SD_CLK/SPI3_MOSI PC12 GPIO_SDIO_CK
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* 6 VSS N/A N/A
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* 7 DAT0/D0 SD_D0/DCMI_D2 PC8 GPIO_SDIO_D0
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* 8 DAT1/RES SD_D1/DCMI_D3 PC9 GPIO_SDIO_D1
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* --- ------------- ----------------- -------------------------
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*
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* NOTES:
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* 1. DAT4, DAT4, DAT6, and DAT7 not connected.
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* 2. There are no alternative pin selections.
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* 3. There is no card detect (CD) GPIO input so we will not
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* sense if there is a card in the SD slot or not. This will
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* make usage very awkward.
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*/
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2016-12-21 18:38:45 +01:00
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/* Ethernet:
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*
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2016-12-21 00:49:46 +01:00
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* - PA2 is ETH_MDIO
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* - PC1 is ETH_MDC
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* - PB5 is ETH_PPS_OUT - NC (not connected)
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* - PA0 is ETH_MII_CRS - NC
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* - PA3 is ETH_MII_COL - NC
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* - PB10 is ETH_MII_RX_ER - NC
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* - PB0 is ETH_MII_RXD2 - NC
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* - PH7 is ETH_MII_RXD3 - NC
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* - PC3 is ETH_MII_TX_CLK - NC
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* - PC2 is ETH_MII_TXD2 - NC
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* - PB8 is ETH_MII_TXD3 - NC
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* - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK
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* - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV
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* - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0
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* - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1
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* - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN
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* - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0
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* - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1
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*/
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#define GPIO_ETH_PPS_OUT GPIO_ETH_PPS_OUT_1
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#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_1
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#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_1
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#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_1
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#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_1
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#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_1
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#define GPIO_ETH_MII_TXD3 GPIO_ETH_MII_TXD3_1
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#define GPIO_ETH_MII_TX_EN GPIO_ETH_MII_TX_EN_2
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#define GPIO_ETH_MII_TXD0 GPIO_ETH_MII_TXD0_2
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#define GPIO_ETH_MII_TXD1 GPIO_ETH_MII_TXD1_2
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|
#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1
|
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|
|
#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
|
|
|
|
|
#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
|
|
|
|
|
|
2020-05-12 22:36:48 +02:00
|
|
|
/* DMA Channel/Stream Selections ********************************************/
|
|
|
|
|
|
|
|
|
|
/* Stream selections are arbitrary for now but might become important in
|
|
|
|
|
* the future if we set aside more DMA channels/streams.
|
2017-01-28 17:17:10 +01:00
|
|
|
*
|
|
|
|
|
* SDIO DMA
|
2018-05-27 02:03:37 +02:00
|
|
|
* DMAMAP_SDIO_1 = Channel 4, Stream 3
|
|
|
|
|
* DMAMAP_SDIO_2 = Channel 4, Stream 6
|
2017-01-28 17:17:10 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define DMAMAP_SDIO DMAMAP_SDIO_1
|
|
|
|
|
|
2018-05-27 02:03:37 +02:00
|
|
|
/* USART6
|
|
|
|
|
*
|
|
|
|
|
* DMAMAP_USART6_RX_1 = Channel 5, Stream1
|
|
|
|
|
* DMAMAP_USART6_RX_2 = Channel 5, Stream2
|
|
|
|
|
* DMAMAP_USART6_TX_1 = Channel 5, Stream6
|
|
|
|
|
* DMAMAP_USART6_TX_2 = Channel 5, Stream7
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1
|
|
|
|
|
#define DMAMAP_USART6_TX DMAMAP_USART6_TX_1
|
|
|
|
|
|
2020-05-12 22:19:26 +02:00
|
|
|
/* DHTxx pin configuration */
|
|
|
|
|
|
|
|
|
|
#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9)
|
|
|
|
|
#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN)
|
|
|
|
|
#define GPIO_DHTXX_PIN_INPUT (GPIO_INPUT|GPIO_FLOAT|GPIO_DHTXX_PIN)
|
|
|
|
|
|
|
|
|
|
#define BOARD_DHTXX_GPIO_INPUT GPIO_DHTXX_PIN_INPUT
|
|
|
|
|
#define BOARD_DHTXX_GPIO_OUTPUT GPIO_DHTXX_PIN_OUTPUT
|
|
|
|
|
#define BOARD_DHTXX_FRTIMER 1 /* Free-run timer 1 */
|
|
|
|
|
|
2020-06-15 15:56:10 +02:00
|
|
|
/* SPI3 - As present in the UEXT header */
|
2020-06-03 16:45:41 +02:00
|
|
|
|
2020-06-15 15:56:10 +02:00
|
|
|
#define GPIO_SPI3_MISO GPIO_SPI3_MISO_2
|
|
|
|
|
#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
|
|
|
|
|
#define GPIO_SPI3_SCK GPIO_SPI3_SCK_2
|
2020-06-03 16:45:41 +02:00
|
|
|
|
|
|
|
|
#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1
|
|
|
|
|
#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1
|
|
|
|
|
|
|
|
|
|
/* I2S3 - CS4344 configuration uses I2S3 */
|
|
|
|
|
|
|
|
|
|
#define GPIO_I2S3_SD GPIO_I2S3_SD_1
|
|
|
|
|
#define GPIO_I2S3_CK GPIO_I2S3_CK_1
|
|
|
|
|
#define GPIO_I2S3_WS GPIO_I2S3_WS_2
|
|
|
|
|
|
|
|
|
|
#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2
|
|
|
|
|
#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2
|
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H */
|
