2017-05-02 14:36:18 +02:00
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/************************************************************************************
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* configs/nucleo-l496zg/include/board.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Mark Olsson <post@markolsson.se>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIG_NUCLEO_L496ZG_INCLUDE_BOARD_H
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#define __CONFIG_NUCLEO_L496ZG_INCLUDE_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#ifdef __KERNEL__
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#include "stm32l4_rcc.h"
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#ifdef CONFIG_STM32L4_SDMMC1
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# include "stm32l4_sdmmc.h"
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#endif
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The Nucleo-144 board provides the following clock sources:
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*
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* MCO: 8 MHz from MCO output of ST-LINK is used as input clock
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* X2: 32.768 KHz crystal for LSE
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* X3: HSE crystal oscillator (not provided)
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: 8 MHz from MCO output of ST-LINK
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* LSE: 32.768 kHz
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*/
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2017-09-20 14:20:45 +02:00
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#define STM32L4_HSI_FREQUENCY 16000000ul
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#define STM32L4_LSI_FREQUENCY 32000
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#define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */
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#define STM32L4_LSE_FREQUENCY 32768
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2017-05-02 14:36:18 +02:00
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#define HSI_CLOCK_CONFIG
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#if defined(HSI_CLOCK_CONFIG)
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#define STM32L4_BOARD_USEHSI
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/* Prescaler common to all PLL inputs; will be 1 */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
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*
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* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
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* the system clock; this should be configurable since not all applications may
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* want things done this way.
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*/
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
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#define STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
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* do that with the main PLL's N value. We set N = 13, and enable
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* the Q output (ultimately for CLK48) with /4. So,
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* 16 MHz / 1 * 12 / 4 = 48 MHz
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*
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* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
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* menuconfig, or else all this is a moot point, and the various 48 MHz
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* peripherals will not work (RNG at present). I would suggest removing
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* that option from Kconfig altogether, and simply making it an option
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* that is selected via a #define here, like all these other params.
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*/
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* CLK48 will come from PLLSAI1 (implicitly Q) */
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#define STM32L4_USE_CLK48 1
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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#define STM32L4_USE_LSE 1
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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2017-08-25 15:02:21 +02:00
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#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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2017-05-02 14:36:18 +02:00
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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2017-08-25 15:02:21 +02:00
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* Note: TIM1,8,15,16,17 are on APB2, others on APB1
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2017-05-02 14:36:18 +02:00
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*/
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/* REVISIT : this can be configured */
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#elif defined(HSE_CLOCK_CONFIG)
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# error "Not implemented"
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#endif
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2017-09-01 09:08:09 +02:00
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8,15,16,17 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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2017-05-02 14:36:18 +02:00
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/* SDMMC dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
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*/
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#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
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* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
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* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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#if defined(CONFIG_STM32L4_SDMMC2)
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# define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1
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# define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1
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# define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1
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# define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1
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#endif
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/* DMA Channel/Stream Selections *****************************************************/
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/* Stream selections are arbitrary for now but might become important in the future
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* if we set aside more DMA channels/streams.
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*
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* SDMMC DMA is on DMA2
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*
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* SDMMC1 DMA
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2017-09-26 14:23:15 +02:00
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* DMAMAP_SDMMC_1 = Channel 4, Stream 7
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* DMAMAP_SDMMC_2 = Channel 5, Stream 7
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2017-05-02 14:36:18 +02:00
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*
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* SDMMC2 DMA
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* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
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* DMAMAP_SDMMC3_2 = Channel 11, Stream 5
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*/
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2017-09-26 14:23:15 +02:00
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#define DMAMAP_SDMMC1 DMACHAN_SDMMC_1
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#define DMAMAP_SDMMC2 DMACHAN_SDMMC_2
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2017-05-02 14:36:18 +02:00
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* LED definitions ******************************************************************/
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/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
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* LED and LD3 a Red LED, that can be controlled by software. The following
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* definitions assume the default Solder Bridges are installed.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_BLUE BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-related
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* events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ----*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions ***************************************************************/
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/* The Nucleo-L496ZG supports one button: Pushbutton B1, labeled "User", is
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* connected to GPIO PC13. A high value will be sensed when the button is depressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ************************************************/
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#define GPIO_USART2_TX GPIO_USART2_TX_2
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#define GPIO_USART2_RX GPIO_USART2_RX_2
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#define GPIO_USART3_TX GPIO_USART3_TX_2
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#define GPIO_USART3_RX GPIO_USART3_RX_2
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#if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO)
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/* USART6:
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*
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* These configurations assume that you are using a standard Arduio RS-232 shield
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* with the serial interface with RX on pin D0 and TX on pin D1:
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*
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* -------- ---------------
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* STM32F7
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* ARDUIONO FUNCTION GPIO
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* -- ----- --------- -----
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* DO RX USART6_RX PG9
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* D1 TX USART6_TX PG14
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* -- ----- --------- -----
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*/
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# define GPIO_USART6_RX GPIO_USART6_RX_2
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# define GPIO_USART6_TX GPIO_USART6_TX_2
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#endif
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/* USART3:
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* Use USART3 and the USB virtual COM port
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*/
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#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
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/* LPUART1 is connector to Virtual COM port PG6 and PG7, but there is no lpserial. */
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//#define GPIO_USART2_TX GPIO_LPUART1_TX_3
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//#define GPIO_USART2_RX GPIO_LPUART1_RX_3
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# error "No Nucleo virtual console before lpserial is unimplemented"
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#endif
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/* DMA channels *************************************************************/
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/* ADC */
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|
2017-08-25 15:02:21 +02:00
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#define ADC1_DMA_CHAN DMACHAN_ADC1_1
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2017-08-30 10:40:58 +02:00
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#define ADC2_DMA_CHAN DMACHAN_ADC2_2
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#define ADC3_DMA_CHAN DMACHAN_ADC3_2
|
2017-05-02 14:36:18 +02:00
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/* SPI
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*
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*
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* PA6 SPI1_MISO CN12-13
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* PA7 SPI1_MOSI CN12-15
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* PA5 SPI1_SCK CN12-11
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*
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* PB14 SPI2_MISO CN12-28
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* PB15 SPI2_MOSI CN12-26
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* PB13 SPI2_SCK CN12-30
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*
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* PB4 SPI3_MISO CN12-27
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* PB5 SPI3_MOSI CN12-29
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* PB3 SPI3_SCK CN12-31
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
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/* I2C
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*
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*
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* PB8 I2C1_SCL CN12-3
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* PB9 I2C1_SDA CN12-5
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* PB10 I2C2_SCL CN11-51
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* PB11 I2C2_SDA CN12-18
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*
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* PA8 I2C3_SCL CN12-23
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* PC9 I2C3_SDA CN12-1
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*
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*/
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
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|
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
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|
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
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|
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
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|
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
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|
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
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|
#define GPIO_I2C4_SCL GPIO_I2C4_SCL_1
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|
|
#define GPIO_I2C4_SDA GPIO_I2C4_SDA_1
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|
|
|
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|
|
/************************************************************************************
|
|
|
|
* Public Data
|
|
|
|
************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
#define EXTERN extern "C"
|
|
|
|
extern "C"
|
|
|
|
{
|
|
|
|
#else
|
|
|
|
#define EXTERN extern
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Public Function Prototypes
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
/************************************************************************************
|
2017-07-22 17:53:29 +02:00
|
|
|
* Name: stm32l4_board_initialize
|
2017-05-02 14:36:18 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* All STM32 architectures must provide the following entry point. This entry point
|
|
|
|
* is called early in the initialization -- after all memory has been configured
|
|
|
|
* and mapped but before any devices have been initialized.
|
|
|
|
*
|
|
|
|
************************************************************************************/
|
|
|
|
|
2017-07-22 17:53:29 +02:00
|
|
|
void stm32l4_board_initialize(void);
|
2017-05-02 14:36:18 +02:00
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* __CONFIG_NUCLEO_L496ZG_INCLUDE_BOARD_H */
|