Fix DMA channel mapping
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2143 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
f04860aa46
commit
0132b1ed6d
@ -40,7 +40,6 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <semaphore.h>
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#include <debug.h>
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#include <errno.h>
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@ -104,63 +103,63 @@ static sem_t g_allocsem;
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static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
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{
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{
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.chan = 0,
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.chan = STM32_DMA1_CHAN1,
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.irq = STM32_IRQ_DMA1CH1,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = 1,
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.chan = STM32_DMA1_CHAN2,
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.irq = STM32_IRQ_DMA1CH2,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = 2,
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.chan = STM32_DMA1_CHAN3,
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.irq = STM32_IRQ_DMA1CH3,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = 3,
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.chan = STM32_DMA1_CHAN4,
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.irq = STM32_IRQ_DMA1CH4,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = 4,
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.chan = STM32_DMA1_CHAN5,
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.irq = STM32_IRQ_DMA1CH5,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
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},
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{
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.chan = 5,
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.chan = STM32_DMA1_CHAN6,
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.irq = STM32_IRQ_DMA1CH6,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
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},
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{
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.chan = 6,
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.chan = STM32_DMA1_CHAN7,
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.irq = STM32_IRQ_DMA1CH7,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
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},
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#if STM32_NDMA > 1
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{
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.chan = 7,
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.chan = STM32_DMA2_CHAN1,
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.irq = STM32_IRQ_DMA2CH1,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = 8,
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.chan = STM32_DMA2_CHAN2,
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.irq = STM32_IRQ_DMA2CH2,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = 9,
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.chan = STM32_DMA2_CHAN3,
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.irq = STM32_IRQ_DMA2CH3,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = 10,
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.chan = STM32_DMA2_CHAN4,
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.irq = STM32_IRQ_DMA2CH4,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = 11,
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.chan = STM32_DMA2_CHAN5,
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.irq = STM32_IRQ_DMA2CH5,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
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},
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@ -203,33 +202,6 @@ static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32 offset, uint
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putreg32(value, dmach->base + offset);
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}
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/************************************************************************************
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* Name: stm32_dmatake() and stm32_dmagive()
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*
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* Description:
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* Take/give semaphore that protects the channel allocation bitset
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*
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************************************************************************************/
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static void stm32_dmatake(void)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&g_allocsem) != 0)
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{
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/* The only case that an error should occur here is if the wait was awakened
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* by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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static inline void stm32_dmagive(void)
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{
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(void)sem_post(&g_allocsem);
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}
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/************************************************************************************
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* Name: stm32_dmainterrupt
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*
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@ -299,10 +271,6 @@ void weak_function stm32_dmainitialize(void)
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{
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int chan;
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/* Initialize the semaphore used to protect the allocation bitset */
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sem_init(&g_allocsem, 0, 1);
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/* Attach DMA interrupt vectors */
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for (chan = 0; chan < DMA_NCHANNELS; chan++)
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@ -322,33 +290,34 @@ void weak_function stm32_dmainitialize(void)
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*
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****************************************************************************/
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DMA_HANDLE stm32_dmachannel(void)
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DMA_HANDLE stm32_dmachannel(int chan)
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{
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struct stm32_dma_s *dmach = NULL;
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int chan;
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int bit;
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irqstate_t flags;
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dma_bitset_t before;
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int bit = (1 << chan);
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/* Make sure that we exclusive access to the DMA bitset */
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DEBUGASSERT(chan < DMA_NCHANNELS);
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stm32_dmatake();
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/* This is essentially a test and set. We simply disable interrupts to
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* create the critical section. This is brutal (but very quich) and assures
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* that we have exclusive access to the allocation bitset
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*/
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/* Try each possible channel */
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flags = irqsave();
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before = g_dmaallocated;
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g_dmaallocated |= bit;
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irq_restore(flags);
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for (chan = 0, bit = 1; chan < DMA_NCHANNELS; chan++, bit <<= 1)
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/* Was this channel been available? */
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if ((before & bit) == 0)
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{
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/* Has this channel been allocated? */
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/* Yes.. then the caller has it, return it */
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if ((g_dmaallocated & bit) == 0)
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{
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/* No.. grab it and return */
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g_dmaallocated |= bit;
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dmach = &g_dma[chan];
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break;
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}
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dmach = &g_dma[chan];
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}
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stm32_dmagive();
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return (DMA_HANDLE)dmach;
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}
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@ -268,6 +268,90 @@
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#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
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#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
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/* DMA Channel mapping. Each DMA channel has a mapping to several possible
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* sources/sinks of data. The requests from peripherals assigned to a channel
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* are simply OR'ed together before entering the DMA block. This means that only
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* one request on a given channel can be enabled at once.
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*/
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#define STM32_DMA1_CHAN1 (0)
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#define STM32_DMA1_CHAN2 (1)
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#define STM32_DMA1_CHAN3 (2)
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#define STM32_DMA1_CHAN4 (3)
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#define STM32_DMA1_CHAN5 (4)
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#define STM32_DMA1_CHAN6 (5)
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#define STM32_DMA1_CHAN7 (6)
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#define STM32_DMA2_CHAN1 (7)
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#define STM32_DMA2_CHAN2 (8)
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#define STM32_DMA2_CHAN3 (1)
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#define STM32_DMA2_CHAN4 (10)
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#define STM32_DMA2_CHAN5 (11)
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#define DMACHAN_ADC1 STM32_DMA1_CHAN1
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#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
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#define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
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#define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
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#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
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#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
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#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
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#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
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#define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
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#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
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#define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
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#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
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#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
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#define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
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#define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
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#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
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#define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
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#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
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#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
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#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
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#define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
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#define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
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#define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
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#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
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#define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
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#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
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#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
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#define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
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#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
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#define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
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#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
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#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
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#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
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#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
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#define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
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#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
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#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
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#define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
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#define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
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#define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
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#define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
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#define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
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#define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
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#define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
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#define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
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#define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
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#define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
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#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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#define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
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#define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
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#define DMACHAN_UART4_RX STM32_DMA2_CHAN3
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#define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
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#define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
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#define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
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#define DMACHAN_SDIO STM32_DMA2_CHAN4
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#define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
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#define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
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#define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
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#define DMACHAN_ADC3 STM32_DMA2_CHAN5
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#define DMACHAN_UART4_TX STM32_DMA2_CHAN5
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#define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
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#define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -501,7 +501,7 @@ EXTERN void weak_function stm32_dmainitialize(void);
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*
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****************************************************************************/
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EXTERN DMA_HANDLE stm32_dmachannel(void);
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EXTERN DMA_HANDLE stm32_dmachannel(int chan);
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/****************************************************************************
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* Name: stm32_dmasetup
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