Separater LPC176x and LPC178x GPIO logic into separate files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5815 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
1b3b5db765
commit
19d2d365a4
@ -4511,3 +4511,7 @@
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lpc17_sspinitialize(). So they had to be renamed (2013-4-01).
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* arch/arm/src/lpc17xx/lpc17_ssp.c: Adapted to work the the LPC178x
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family (2013-4-01).
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* arch/arm/src/lpc17xx/lpc17_gpio.c/.h: Separate LPC176x and LPC178x
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logic into separate files. The logic is diverging to much to
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try to retain common code (2013-4-03).
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684
arch/arm/src/lpc17xx/lpc176x_gpio.c
Normal file
684
arch/arm/src/lpc17xx/lpc176x_gpio.c
Normal file
@ -0,0 +1,684 @@
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc176x_gpio.c
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*
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "lpc17_gpio.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Default input pin configuration */
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#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* These tables have global scope because they are also used in
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* lpc17_gpiodbg.c
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*/
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/* We have to remember the configured interrupt setting.. PINs are not
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* actually set up to interrupt until the interrupt is enabled.
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*/
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#ifdef CONFIG_GPIO_IRQ
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uint64_t g_intedge0;
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uint64_t g_intedge2;
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#endif
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/* FIO register base addresses */
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const uint32_t g_fiobase[GPIO_NPORTS] =
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{
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LPC17_FIO0_BASE,
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LPC17_FIO1_BASE,
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LPC17_FIO2_BASE,
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LPC17_FIO3_BASE,
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LPC17_FIO4_BASE
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#if GPIO_NPORTS > 5
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, LPC17_FIO5_BASE
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#endif
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};
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/* Port 0 and Port 2 can provide a single interrupt for any combination of
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* port pins
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*/
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const uint32_t g_intbase[GPIO_NPORTS] =
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{
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LPC17_GPIOINT0_BASE,
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0,
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LPC17_GPIOINT2_BASE,
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0,
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0
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_lopinsel[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINSEL0,
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LPC17_PINCONN_PINSEL2,
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LPC17_PINCONN_PINSEL4,
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0,
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0
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_hipinsel[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINSEL1,
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LPC17_PINCONN_PINSEL3,
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0,
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LPC17_PINCONN_PINSEL7,
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LPC17_PINCONN_PINSEL9
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_lopinmode[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINMODE0,
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LPC17_PINCONN_PINMODE2,
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LPC17_PINCONN_PINMODE4,
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0,
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0
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_hipinmode[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINMODE1,
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LPC17_PINCONN_PINMODE3,
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0,
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LPC17_PINCONN_PINMODE7,
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LPC17_PINCONN_PINMODE9
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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const uint32_t g_odmode[GPIO_NPORTS] =
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{
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LPC17_PINCONN_ODMODE0,
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LPC17_PINCONN_ODMODE1,
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LPC17_PINCONN_ODMODE2,
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LPC17_PINCONN_ODMODE3,
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LPC17_PINCONN_ODMODE4
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#if GPIO_NPORTS > 5
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, 0
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc17_pinsel
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*
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* Description:
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* Get the address of the PINSEL register corresponding to this port and
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* pin number.
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*
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****************************************************************************/
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static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value)
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{
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const uint32_t *table;
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uint32_t regaddr;
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uint32_t regval;
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unsigned int shift;
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/* Which table do we use */
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if (pin < 16)
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{
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table = g_lopinsel;
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shift = PINCONN_PINSELL_SHIFT(pin);
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}
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else
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{
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table = g_hipinsel;
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shift = PINCONN_PINSELH_SHIFT(pin);
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}
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/* Fetch the PINSEL register address for this port/pin combination */
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regaddr = table[port];
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if (regaddr != 0)
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{
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/* Set the requested value in the PINSEL register */
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regval = getreg32(regaddr);
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regval &= ~(PINCONN_PINSEL_MASK << shift);
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regval |= (value << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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* Name: lpc17_pullup
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*
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* Description:
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* Get the address of the PINMODE register corresponding to this port and
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* pin number.
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*
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****************************************************************************/
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static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port,
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unsigned int pin)
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{
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const uint32_t *table;
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uint32_t regaddr;
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uint32_t regval;
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uint32_t value;
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unsigned int shift;
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switch (cfgset & GPIO_PUMODE_MASK)
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{
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default:
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case GPIO_PULLUP: /* Pull-up resistor enabled */
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value = PINCONN_PINMODE_PU;
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break;
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case GPIO_REPEATER: /* Repeater mode enabled */
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value = PINCONN_PINMODE_RM;
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break;
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case GPIO_FLOAT: /* Neither pull-up nor -down */
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value = PINCONN_PINMODE_FLOAT;
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break;
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case GPIO_PULLDN: /* Pull-down resistor enabled */
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value = PINCONN_PINMODE_PD;
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break;
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}
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/* Which table do we use */
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if (pin < 16)
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{
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table = g_lopinmode;
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shift = PINCONN_PINMODEL_SHIFT(pin);
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}
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else
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{
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table = g_hipinmode;
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shift = PINCONN_PINMODEH_SHIFT(pin);
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}
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/* Fetch the PINSEL register address for this port/pin combination */
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regaddr = table[port];
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if (regaddr != 0)
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{
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/* Set the requested value in the PINSEL register */
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regval = getreg32(regaddr);
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regval &= ~(PINCONN_PINMODE_MASK << shift);
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regval |= (value << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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* Name: lpc17_setintedge
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*
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* Description:
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* Remember the configured interrupt edge. We can't actually enable the
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* the edge interrupts until the called calls IRQ enabled function.
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*
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****************************************************************************/
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#ifdef CONFIG_GPIO_IRQ
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static void lpc17_setintedge(unsigned int port, unsigned int pin,
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unsigned int value)
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{
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uint64_t *intedge;
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unsigned int shift;
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/* Which word to we use? */
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if (port == 0)
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{
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intedge = &g_intedge0;
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}
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else if (port == 2)
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{
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intedge = &g_intedge2;
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}
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else
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{
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return;
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}
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/* Set the requested value in the PINSEL register */
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shift = pin << 1;
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*intedge &= ~((uint64_t)3 << shift);
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*intedge |= ((uint64_t)value << shift);
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}
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#endif /* CONFIG_GPIO_IRQ */
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/****************************************************************************
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* Name: lpc17_setopendrain
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*
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* Description:
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* Set the ODMODE register for open drain mode
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*
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****************************************************************************/
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static void lpc17_setopendrain(unsigned int port, unsigned int pin)
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{
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uint32_t regaddr;
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uint32_t regval;
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regaddr = g_odmode[port];
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regval = getreg32(regaddr);
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regval |= (1 << pin);
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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* Name: lpc17_clropendrain
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*
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* Description:
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* Reset the ODMODE register to disable open drain mode
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*
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****************************************************************************/
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static void lpc17_clropendrain(unsigned int port, unsigned int pin)
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{
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uint32_t regaddr;
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uint32_t regval;
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regaddr = g_odmode[port];
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regval = getreg32(regaddr);
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regval &= ~(1 << pin);
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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* Name: lpc17_configinput
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*
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* Description:
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* Configure a GPIO inpue pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin)
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{
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uint32_t regval;
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uint32_t fiobase;
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uint32_t intbase;
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uint32_t pinmask = (1 << pin);
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/* Set up FIO registers */
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fiobase = g_fiobase[port];
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/* Set as input */
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regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
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regval &= ~pinmask;
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putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
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/* Set up interrupt registers */
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intbase = g_intbase[port];
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if (intbase != 0)
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{
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/* Disable any rising edge interrupts */
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regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
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regval &= ~pinmask;
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putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
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/* Disable any falling edge interrupts */
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regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
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regval &= ~pinmask;
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putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
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/* Forget about any falling/rising edge interrupt enabled */
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#ifdef CONFIG_GPIO_IRQ
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lpc17_setintedge(port, pin, 0);
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#endif
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}
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/* Set up PINSEL registers */
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/* Configure as GPIO */
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lpc17_pinsel(port, pin, PINCONN_PINSEL_GPIO);
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/* Set pull-up mode */
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lpc17_pullup(cfgset, port, pin);
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/* Open drain only applies to outputs */
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lpc17_clropendrain(port, pin);
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return OK;
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}
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/****************************************************************************
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* Name: lpc17_configinterrupt
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*
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* Description:
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* Configure a GPIO interrupt pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port,
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unsigned int pin)
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{
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/* First, configure the port as a generic input so that we have a known
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* starting point and consistent behavior during the re-configuration.
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*/
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(void)lpc17_configinput(cfgset, port, pin);
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/* Then just remember the rising/falling edge interrupt enabled */
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DEBUGASSERT(port == 0 || port == 2);
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#ifdef CONFIG_GPIO_IRQ
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lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
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#endif
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return OK;
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}
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/****************************************************************************
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* Name: lpc17_configoutput
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*
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* Description:
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* Configure a GPIO output pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port,
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unsigned int pin)
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{
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uint32_t fiobase;
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uint32_t regval;
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/* First, configure the port as a generic input so that we have a known
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* starting point and consistent behavior during the re-configuration.
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*/
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(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
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/* Now, reconfigure the pin as an output */
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fiobase = g_fiobase[port];
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regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
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regval |= (1 << pin);
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putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
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/* Check for open drain output */
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if ((cfgset & GPIO_OPEN_DRAIN) != 0)
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{
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/* Set pull-up mode. This normally only applies to input pins, but does have
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* meaning if the port is an open drain output.
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*/
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lpc17_pullup(cfgset, port, pin);
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/* Select open drain output */
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lpc17_setopendrain(port, pin);
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}
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/* Set the initial value of the output */
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lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO));
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return OK;
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}
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/****************************************************************************
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* Name: lpc17_configalternate
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*
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* Description:
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* Configure a GPIO alternate function pin based on bit-encoded description
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* of the pin.
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*
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****************************************************************************/
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static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
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unsigned int pin, uint32_t alt)
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{
|
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/* First, configure the port as an input so that we have a known
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* starting point and consistent behavior during the re-configuration.
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*/
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(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
|
||||
|
||||
/* Set up PINSEL registers */
|
||||
/* Configure as GPIO */
|
||||
|
||||
lpc17_pinsel(port, pin, alt);
|
||||
|
||||
/* Set pull-up mode */
|
||||
|
||||
lpc17_pullup(cfgset, port, pin);
|
||||
|
||||
/* Check for open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
/* Select open drain output */
|
||||
|
||||
lpc17_setopendrain(port, pin);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc17_configgpio(lpc17_pinset_t cfgset)
|
||||
{
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
int ret = -EINVAL;
|
||||
|
||||
/* Verify that this hardware supports the select GPIO port */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the pin number and select the port configuration register for that pin */
|
||||
|
||||
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Handle according to pin function */
|
||||
|
||||
switch (cfgset & GPIO_FUNC_MASK)
|
||||
{
|
||||
case GPIO_INPUT: /* GPIO input pin */
|
||||
ret = lpc17_configinput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
ret = lpc17_configinterrupt(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT: /* GPIO outpout pin */
|
||||
ret = lpc17_configoutput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_ALT1: /* Alternate function 1 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2: /* Alternate function 2 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3: /* Alternate function 3 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
uint32_t offset;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
{
|
||||
offset = LPC17_FIO_SET_OFFSET;
|
||||
}
|
||||
else
|
||||
{
|
||||
offset = LPC17_FIO_CLR_OFFSET;
|
||||
}
|
||||
|
||||
putreg32((1 << pin), fiobase + offset);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool lpc17_gpioread(lpc17_pinset_t pinset)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
197
arch/arm/src/lpc17xx/lpc176x_gpio.h
Normal file
197
arch/arm/src/lpc17xx/lpc176x_gpio.h
Normal file
@ -0,0 +1,197 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc176x_gpio.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC176X_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC176X_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Bit-encoded input to lpc17_configgpio() ******************************************/
|
||||
|
||||
/* Encoding: FFFx MMOV PPPN NNNN
|
||||
*
|
||||
* Pin Function: FFF
|
||||
* Pin Mode bits: MM
|
||||
* Open drain: O (output pins)
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PPP (0-4)
|
||||
* Pin number: NNNNN (0-31)
|
||||
*/
|
||||
|
||||
/* Pin Function bits: FFF
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
|
||||
#define GPIO_FUNC_SHIFT (13) /* Bits 13-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT)
|
||||
#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0)
|
||||
|
||||
/* Pin Mode: MM */
|
||||
|
||||
#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
|
||||
# define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
|
||||
# define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
|
||||
# define GPIO_FLOAT (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
|
||||
# define GPIO_PULLDN (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
|
||||
|
||||
/* Open drain: O */
|
||||
|
||||
#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */
|
||||
|
||||
/* Initial value: V */
|
||||
|
||||
#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */
|
||||
#define GPIO_VALUE_ONE GPIO_VALUE
|
||||
#define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PPP (0-4) */
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_NPORTS 5
|
||||
|
||||
/* Pin number: NNNNN (0-31) */
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
typedef uint16_t lpc17_pinset_t;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* These tables have global scope only because they are shared between lpc17_gpio.c,
|
||||
* lpc17_gpioint.c, and lpc17_gpiodbg.c
|
||||
*/
|
||||
|
||||
EXTERN const uint32_t g_lopinsel[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_hipinsel[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_lopinmode[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_hipinmode[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_odmode[GPIO_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC176X_GPIO_H */
|
||||
631
arch/arm/src/lpc17xx/lpc178x_gpio.c
Normal file
631
arch/arm/src/lpc17xx/lpc178x_gpio.c
Normal file
@ -0,0 +1,631 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc178x_gpio.c
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* With LPC178x extensions from Rommel Marcelo
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "lpc17_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Default input pin configuration */
|
||||
|
||||
#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
/* These tables have global scope because they are also used in
|
||||
* lpc17_gpiodbg.c
|
||||
*/
|
||||
|
||||
/* We have to remember the configured interrupt setting.. PINs are not
|
||||
* actually set up to interrupt until the interrupt is enabled.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
uint64_t g_intedge0;
|
||||
uint64_t g_intedge2;
|
||||
#endif
|
||||
|
||||
/* FIO register base addresses */
|
||||
|
||||
const uint32_t g_fiobase[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_FIO0_BASE,
|
||||
LPC17_FIO1_BASE,
|
||||
LPC17_FIO2_BASE,
|
||||
LPC17_FIO3_BASE,
|
||||
LPC17_FIO4_BASE
|
||||
#if GPIO_NPORTS > 5
|
||||
, LPC17_FIO5_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Port 0 and Port 2 can provide a single interrupt for any combination of
|
||||
* port pins
|
||||
*/
|
||||
|
||||
const uint32_t g_intbase[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_GPIOINT0_BASE,
|
||||
0,
|
||||
LPC17_GPIOINT2_BASE,
|
||||
0,
|
||||
0
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configiocon
|
||||
*
|
||||
* Description:
|
||||
* Set the LPC178x IOCON register
|
||||
*
|
||||
* Type D: FUNC, MODE, HYS, INV, SLEW, OD -
|
||||
* Type A: FUNC, MODE, INV, ADMODE, FILTER, OD, DACEN -P0[12:13,23:26],P1[30:31]
|
||||
* Type U: FUNC -P0[29:31]
|
||||
* Type I: FUNC, INV, HS, HIDRIVE -P0[27:28], P5[2:3]
|
||||
* Type W: FUNC, MODE, HYS, INV, FILTER, SLEW, OD -P0[7:9]
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int lpc17_configiocon(unsigned int port, unsigned int pin,
|
||||
unsigned int value)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t typemask = GPIO_IOCON_TYPE_D_MASK;
|
||||
|
||||
/* Select the mask based on pin usage */
|
||||
|
||||
switch (port)
|
||||
{
|
||||
case 0:
|
||||
switch (pin)
|
||||
{
|
||||
case 7:
|
||||
case 8:
|
||||
case 9:
|
||||
typemask = GPIO_IOCON_TYPE_W_MASK;
|
||||
break;
|
||||
|
||||
case 12:
|
||||
case 13:
|
||||
case 23:
|
||||
case 24:
|
||||
case 25:
|
||||
case 26:
|
||||
typemask = GPIO_IOCON_TYPE_A_MASK;
|
||||
break;
|
||||
|
||||
case 27:
|
||||
case 28:
|
||||
typemask = GPIO_IOCON_TYPE_I_MASK;
|
||||
break;
|
||||
|
||||
case 29:
|
||||
case 30:
|
||||
case 31:
|
||||
typemask = GPIO_IOCON_TYPE_U_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
switch (pin)
|
||||
{
|
||||
case 30:
|
||||
case 31:
|
||||
typemask = GPIO_IOCON_TYPE_A_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 5:
|
||||
switch (pin)
|
||||
{
|
||||
case 2:
|
||||
case 3:
|
||||
typemask = GPIO_IOCON_TYPE_I_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
regaddr = LPC17_IOCON_P(port, pin);
|
||||
regval = getreg32(regaddr);
|
||||
regval |= value;
|
||||
regval &= typemask;
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_setintedge
|
||||
*
|
||||
* Description:
|
||||
* Remember the configured interrupt edge. We can't actually enable the
|
||||
* the edge interrupts until the called calls IRQ enabled function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
static void lpc17_setintedge(unsigned int port, unsigned int pin,
|
||||
unsigned int value)
|
||||
{
|
||||
uint64_t *intedge;
|
||||
unsigned int shift;
|
||||
|
||||
/* Which word to we use? */
|
||||
|
||||
if (port == 0)
|
||||
{
|
||||
intedge = &g_intedge0;
|
||||
}
|
||||
else if (port == 2)
|
||||
{
|
||||
intedge = &g_intedge2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set the requested value in the PINSEL register */
|
||||
|
||||
shift = pin << 1;
|
||||
*intedge &= ~((uint64_t)3 << shift);
|
||||
*intedge |= ((uint64_t)value << shift);
|
||||
}
|
||||
#endif /* CONFIG_GPIO_IRQ */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configinput
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO inpue pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t fiobase;
|
||||
uint32_t intbase;
|
||||
uint32_t pinmask = (1 << pin);
|
||||
|
||||
/* Set up FIO registers */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Set as input */
|
||||
|
||||
regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
regval &= ~pinmask;
|
||||
putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
|
||||
/* Set up interrupt registers */
|
||||
|
||||
intbase = g_intbase[port];
|
||||
if (intbase != 0)
|
||||
{
|
||||
/* Disable any rising edge interrupts */
|
||||
|
||||
regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
|
||||
regval &= ~pinmask;
|
||||
putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
|
||||
|
||||
/* Disable any falling edge interrupts */
|
||||
|
||||
regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
|
||||
regval &= ~pinmask;
|
||||
putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
|
||||
|
||||
/* Forget about any falling/rising edge interrupt enabled */
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc17_setintedge(port, pin, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set up PINSEL registers */
|
||||
/* Configure the pin as a GPIO. Clear opendrain, input inversion,
|
||||
* hysteris, slew. Set analog pins as digital.
|
||||
*/
|
||||
|
||||
regval = IOCON_FUNC_GPIO;
|
||||
|
||||
/* Set pull-up mode. Isolate the field from the cfgset and move it
|
||||
* into the correct position in the register value.
|
||||
*/
|
||||
|
||||
regval |= (((cfgset & GPIO_PUMODE_MASK) >> GPIO_PUMODE_SHIFT) << IOCON_MODE_SHIFT);
|
||||
|
||||
/* Select input polarity */
|
||||
|
||||
if ((cfgset & GPIO_INVERT) != 0)
|
||||
{
|
||||
regval |= IOCON_INV_MASK;
|
||||
}
|
||||
|
||||
/* Select hysteresis enable */
|
||||
|
||||
if ((cfgset & GPIO_HYSTERESIS) != 0)
|
||||
{
|
||||
regval |= IOCON_HYS_MASK;
|
||||
}
|
||||
|
||||
/* Set IOCON register */
|
||||
|
||||
lpc17_configiocon(port, pin, regval);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configinterrupt
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO interrupt pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin)
|
||||
{
|
||||
/* First, configure the port as a generic input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(cfgset, port, pin);
|
||||
|
||||
/* Then just remember the rising/falling edge interrupt enabled */
|
||||
|
||||
DEBUGASSERT(port == 0 || port == 2);
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configoutput
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO output pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
uint32_t regval;
|
||||
|
||||
/* First, configure the port as a generic input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
|
||||
|
||||
/* Now, reconfigure the pin as an output */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
regval |= (1 << pin);
|
||||
putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
|
||||
/* Configure the pin as a GPIO. Clear opendrain, input inversion,
|
||||
* hysteris, slew. Set analog pins as digital.
|
||||
*/
|
||||
|
||||
regval = IOCON_FUNC_GPIO;
|
||||
|
||||
/* Select open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
regval |= IOCON_OD_MASK;
|
||||
}
|
||||
|
||||
/* Select slew output */
|
||||
|
||||
if ((cfgset & GPIO_SLEW) != 0)
|
||||
{
|
||||
regval |= IOCON_SLEW_MASK;
|
||||
}
|
||||
|
||||
/* Set pull-up mode. Isolate the field from the cfgset and move it
|
||||
* into the correct position in the register value.
|
||||
*/
|
||||
|
||||
regval |= (((cfgset & GPIO_PUMODE_MASK) >> GPIO_PUMODE_SHIFT) << IOCON_MODE_SHIFT);
|
||||
|
||||
/* Set IOCON register */
|
||||
|
||||
lpc17_configiocon(port, pin, regval);
|
||||
|
||||
/* Set the initial value of the output */
|
||||
|
||||
lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO));
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configalternate
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO alternate function pin based on bit-encoded description
|
||||
* of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin, uint32_t alt)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* First, configure the port as an input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
|
||||
|
||||
/* Select the alternate pin */
|
||||
|
||||
regval = (alt & IOCON_FUNC_MASK);
|
||||
|
||||
/* Select analog mode */
|
||||
|
||||
if ((cfgset & GPIO_ADMODE) != 0)
|
||||
{
|
||||
regval |= IOCON_ADMODE_MASK;
|
||||
}
|
||||
|
||||
/* Set pull-up mode. Isolate the field from the cfgset and move it
|
||||
* into the correct position in the register value.
|
||||
*/
|
||||
|
||||
regval |= (((cfgset & GPIO_PUMODE_MASK) >> GPIO_PUMODE_SHIFT) << IOCON_MODE_SHIFT);
|
||||
|
||||
/* Select open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
regval |= IOCON_OD_MASK;
|
||||
}
|
||||
|
||||
/* Set IOCON register */
|
||||
|
||||
lpc17_configiocon(port, pin, regval);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc17_configgpio(lpc17_pinset_t cfgset)
|
||||
{
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
int ret = -EINVAL;
|
||||
|
||||
/* Verify that this hardware supports the select GPIO port */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the pin number and select the port configuration register for that pin */
|
||||
|
||||
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Handle according to pin function */
|
||||
|
||||
switch (cfgset & GPIO_FUNC_MASK)
|
||||
{
|
||||
case GPIO_INPUT: /* GPIO input pin */
|
||||
ret = lpc17_configinput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
ret = lpc17_configinterrupt(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT: /* GPIO outpout pin */
|
||||
ret = lpc17_configoutput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_ALT1: /* Alternate function 1 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2: /* Alternate function 2 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3: /* Alternate function 3 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3);
|
||||
break;
|
||||
|
||||
case GPIO_ALT4: /* Alternate function 4 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT4);
|
||||
break;
|
||||
|
||||
case GPIO_ALT5: /* Alternate function 5 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT5);
|
||||
break;
|
||||
|
||||
case GPIO_ALT6: /* Alternate function 6 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT6);
|
||||
break;
|
||||
|
||||
case GPIO_ALT7: /* Alternate function 7 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT7);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
uint32_t offset;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
{
|
||||
offset = LPC17_FIO_SET_OFFSET;
|
||||
}
|
||||
else
|
||||
{
|
||||
offset = LPC17_FIO_CLR_OFFSET;
|
||||
}
|
||||
|
||||
putreg32((1 << pin), fiobase + offset);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool lpc17_gpioread(lpc17_pinset_t pinset)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
219
arch/arm/src/lpc17xx/lpc178x_gpio.h
Normal file
219
arch/arm/src/lpc17xx/lpc178x_gpio.h
Normal file
@ -0,0 +1,219 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc178x_gpio.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC178X_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC178X_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Bit-encoded input to lpc17_configgpio() ******************************************/
|
||||
|
||||
/* Encoding: TTTT TTTT FFFF MMOV PPPN NNNN
|
||||
*
|
||||
* Special Pin Functions: TTTT TTTT
|
||||
* Pin Function: FFFF
|
||||
* Pin Mode bits: MM
|
||||
* Open drain: O (output pins)
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PPP (0-4)
|
||||
* Pin number: NNNNN (0-31)
|
||||
*/
|
||||
|
||||
/* Special Pin Functions
|
||||
* For pins that has ADC/DAC, USB, I2C
|
||||
*/
|
||||
|
||||
#define GPIO_IOCON_TYPE_D_MASK (0x0000067f) /* All port except where ADC/DAC, USB, I2C is present */
|
||||
#define GPIO_IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */
|
||||
#define GPIO_IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */
|
||||
#define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */
|
||||
#define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
|
||||
|
||||
#define GPIO_IOCON_MASK (0x00ff0000)
|
||||
# define GPIO_HYSTERESIS (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */
|
||||
# define GPIO_INVERT (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */
|
||||
# define GPIO_SLEW (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */
|
||||
# define GPIO_ADMODE (1 << 19) /* Bit 19: A/D Modes: 0-Analog, 1-Digital */
|
||||
# define GPIO_FILTER (1 << 20) /* Bit 20: Filter: 0-Off, 1-ON */
|
||||
# define GPIO_DACEN (1 << 21) /* Bit 21: DAC: 0-Disabled, 1-Enabled, P0:26 only */
|
||||
# define GPIO_I2CHS (1 << 22) /* Bit 22: Filter and Rate Control: 0-Enabled, 1-Disabled */
|
||||
# define GPIO_HIDRIVE (1 << 23) /* Bit 23: Current Sink: 0-4mA, 1-20mA P5:2 and P5:3 only,*/
|
||||
|
||||
/* Pin Function bits: FFFF
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
|
||||
#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO outpout pin */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */
|
||||
# define GPIO_ALT4 (8 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 4 */
|
||||
# define GPIO_ALT5 (9 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 5 */
|
||||
# define GPIO_ALT6 (10 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 6 */
|
||||
# define GPIO_ALT7 (11 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 7 */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (12) /* Bits 12-13: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT)
|
||||
#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0)
|
||||
|
||||
/* Pin Mode: MM */
|
||||
|
||||
#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
|
||||
# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
|
||||
# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
|
||||
# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
|
||||
# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
|
||||
|
||||
/* Open drain: O */
|
||||
|
||||
#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */
|
||||
|
||||
/* Initial value: V */
|
||||
|
||||
#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */
|
||||
# define GPIO_VALUE_ONE GPIO_VALUE
|
||||
# define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PPP (0-5) */
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_NPORTS 6
|
||||
|
||||
/* Pin number: NNNNN (0-31) */
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
typedef uint32_t lpc17_pinset_t;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* These tables have global scope only because they are shared between lpc17_gpio.c,
|
||||
* lpc17_gpioint.c, and lpc17_gpiodbg.c
|
||||
*/
|
||||
|
||||
EXTERN const uint32_t g_ioconport[GPIO_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC178X_GPIO_H */
|
||||
@ -40,26 +40,26 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
/* This file is only a thin shell that includes the correct GPIO logic for
|
||||
* the selected LPC17xx family. The correct file cannot be selected by the
|
||||
* make system because it needs the intelligence that only exists in chip.h
|
||||
* that can associate an LPC17xx part number with an LPC17xx family.
|
||||
*/
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include <arch/lpc17xx/chip.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "lpc17_gpio.h"
|
||||
#if defined(LPC176x)
|
||||
# include "lpc176x_gpio.c"
|
||||
#elif defined(LPC178x)
|
||||
# include "lpc178x_gpio.c"
|
||||
#else
|
||||
# error "Unrecognized LPC17xx family"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Default input pin configuration */
|
||||
|
||||
#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
@ -71,853 +71,11 @@
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
/* These tables have global scope because they are also used in
|
||||
* lpc17_gpiodbg.c
|
||||
*/
|
||||
|
||||
/* We have to remember the configured interrupt setting.. PINs are not
|
||||
* actually set up to interrupt until the interrupt is enabled.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
uint64_t g_intedge0;
|
||||
uint64_t g_intedge2;
|
||||
#endif
|
||||
|
||||
/* FIO register base addresses */
|
||||
|
||||
const uint32_t g_fiobase[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_FIO0_BASE,
|
||||
LPC17_FIO1_BASE,
|
||||
LPC17_FIO2_BASE,
|
||||
LPC17_FIO3_BASE,
|
||||
LPC17_FIO4_BASE
|
||||
#if GPIO_NPORTS > 5
|
||||
, LPC17_FIO5_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Port 0 and Port 2 can provide a single interrupt for any combination of
|
||||
* port pins
|
||||
*/
|
||||
|
||||
const uint32_t g_intbase[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_GPIOINT0_BASE,
|
||||
0,
|
||||
LPC17_GPIOINT2_BASE,
|
||||
0,
|
||||
0
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef LPC176x
|
||||
const uint32_t g_lopinsel[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_PINCONN_PINSEL0,
|
||||
LPC17_PINCONN_PINSEL2,
|
||||
LPC17_PINCONN_PINSEL4,
|
||||
0,
|
||||
0
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
|
||||
const uint32_t g_hipinsel[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_PINCONN_PINSEL1,
|
||||
LPC17_PINCONN_PINSEL3,
|
||||
0,
|
||||
LPC17_PINCONN_PINSEL7,
|
||||
LPC17_PINCONN_PINSEL9
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
|
||||
const uint32_t g_lopinmode[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_PINCONN_PINMODE0,
|
||||
LPC17_PINCONN_PINMODE2,
|
||||
LPC17_PINCONN_PINMODE4,
|
||||
0,
|
||||
0
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
|
||||
const uint32_t g_hipinmode[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_PINCONN_PINMODE1,
|
||||
LPC17_PINCONN_PINMODE3,
|
||||
0,
|
||||
LPC17_PINCONN_PINMODE7,
|
||||
LPC17_PINCONN_PINMODE9
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
|
||||
const uint32_t g_odmode[GPIO_NPORTS] =
|
||||
{
|
||||
LPC17_PINCONN_ODMODE0,
|
||||
LPC17_PINCONN_ODMODE1,
|
||||
LPC17_PINCONN_ODMODE2,
|
||||
LPC17_PINCONN_ODMODE3,
|
||||
LPC17_PINCONN_ODMODE4
|
||||
#if GPIO_NPORTS > 5
|
||||
, 0
|
||||
#endif
|
||||
};
|
||||
#endif /* LPC176x */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configiocon
|
||||
*
|
||||
* Description:
|
||||
* Set the LPC178x IOCON register
|
||||
*
|
||||
* Type D: FUNC, MODE, HYS, INV, SLEW, OD -
|
||||
* Type A: FUNC, MODE, INV, ADMODE, FILTER, OD, DACEN -P0[12:13,23:26],P1[30:31]
|
||||
* Type U: FUNC -P0[29:31]
|
||||
* Type I: FUNC, INV, HS, HIDRIVE -P0[27:28], P5[2:3]
|
||||
* Type W: FUNC, MODE, HYS, INV, FILTER, SLEW, OD -P0[7:9]
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC178x
|
||||
static int lpc17_configiocon(unsigned int port, unsigned int pin,
|
||||
unsigned int value)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t typemask = GPIO_IOCON_TYPE_D_MASK;
|
||||
|
||||
/* Select the mask based on pin usage */
|
||||
|
||||
switch (port)
|
||||
{
|
||||
case 0:
|
||||
switch (pin)
|
||||
{
|
||||
case 7:
|
||||
case 8:
|
||||
case 9:
|
||||
typemask = GPIO_IOCON_TYPE_W_MASK;
|
||||
break;
|
||||
|
||||
case 12:
|
||||
case 13:
|
||||
case 23:
|
||||
case 24:
|
||||
case 25:
|
||||
case 26:
|
||||
typemask = GPIO_IOCON_TYPE_A_MASK;
|
||||
break;
|
||||
|
||||
case 27:
|
||||
case 28:
|
||||
typemask = GPIO_IOCON_TYPE_I_MASK;
|
||||
break;
|
||||
|
||||
case 29:
|
||||
case 30:
|
||||
case 31:
|
||||
typemask = GPIO_IOCON_TYPE_U_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
switch (pin)
|
||||
{
|
||||
case 30:
|
||||
case 31:
|
||||
typemask = GPIO_IOCON_TYPE_A_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 5:
|
||||
switch (pin)
|
||||
{
|
||||
case 2:
|
||||
case 3:
|
||||
typemask = GPIO_IOCON_TYPE_I_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
regaddr = LPC17_IOCON_P(port, pin);
|
||||
regval = getreg32(regaddr);
|
||||
regval |= value;
|
||||
regval &= typemask;
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif /* LPC178x */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_pinsel
|
||||
*
|
||||
* Description:
|
||||
* Get the address of the PINSEL register corresponding to this port and
|
||||
* pin number.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC176x
|
||||
static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value)
|
||||
{
|
||||
const uint32_t *table;
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
unsigned int shift;
|
||||
|
||||
/* Which table do we use */
|
||||
|
||||
if (pin < 16)
|
||||
{
|
||||
table = g_lopinsel;
|
||||
shift = PINCONN_PINSELL_SHIFT(pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
table = g_hipinsel;
|
||||
shift = PINCONN_PINSELH_SHIFT(pin);
|
||||
}
|
||||
|
||||
/* Fetch the PINSEL register address for this port/pin combination */
|
||||
|
||||
regaddr = table[port];
|
||||
if (regaddr != 0)
|
||||
{
|
||||
/* Set the requested value in the PINSEL register */
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~(PINCONN_PINSEL_MASK << shift);
|
||||
regval |= (value << shift);
|
||||
putreg32(regval, regaddr);
|
||||
return OK;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_pullup
|
||||
*
|
||||
* Description:
|
||||
* Get the address of the PINMODE register corresponding to this port and
|
||||
* pin number.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin)
|
||||
{
|
||||
const uint32_t *table;
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t value;
|
||||
unsigned int shift;
|
||||
|
||||
switch (cfgset & GPIO_PUMODE_MASK)
|
||||
{
|
||||
default:
|
||||
case GPIO_PULLUP: /* Pull-up resistor enabled */
|
||||
value = PINCONN_PINMODE_PU;
|
||||
break;
|
||||
|
||||
case GPIO_REPEATER: /* Repeater mode enabled */
|
||||
value = PINCONN_PINMODE_RM;
|
||||
break;
|
||||
|
||||
case GPIO_FLOAT: /* Neither pull-up nor -down */
|
||||
value = PINCONN_PINMODE_FLOAT;
|
||||
break;
|
||||
|
||||
case GPIO_PULLDN: /* Pull-down resistor enabled */
|
||||
value = PINCONN_PINMODE_PD;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Which table do we use */
|
||||
|
||||
if (pin < 16)
|
||||
{
|
||||
table = g_lopinmode;
|
||||
shift = PINCONN_PINMODEL_SHIFT(pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
table = g_hipinmode;
|
||||
shift = PINCONN_PINMODEH_SHIFT(pin);
|
||||
}
|
||||
|
||||
/* Fetch the PINSEL register address for this port/pin combination */
|
||||
|
||||
regaddr = table[port];
|
||||
if (regaddr != 0)
|
||||
{
|
||||
/* Set the requested value in the PINSEL register */
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~(PINCONN_PINMODE_MASK << shift);
|
||||
regval |= (value << shift);
|
||||
putreg32(regval, regaddr);
|
||||
return OK;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif /* LPC176x */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_setintedge
|
||||
*
|
||||
* Description:
|
||||
* Remember the configured interrupt edge. We can't actually enable the
|
||||
* the edge interrupts until the called calls IRQ enabled function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
static void lpc17_setintedge(unsigned int port, unsigned int pin,
|
||||
unsigned int value)
|
||||
{
|
||||
uint64_t *intedge;
|
||||
unsigned int shift;
|
||||
|
||||
/* Which word to we use? */
|
||||
|
||||
if (port == 0)
|
||||
{
|
||||
intedge = &g_intedge0;
|
||||
}
|
||||
else if (port == 2)
|
||||
{
|
||||
intedge = &g_intedge2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set the requested value in the PINSEL register */
|
||||
|
||||
shift = pin << 1;
|
||||
*intedge &= ~((uint64_t)3 << shift);
|
||||
*intedge |= ((uint64_t)value << shift);
|
||||
}
|
||||
#endif /* CONFIG_GPIO_IRQ */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_setopendrain
|
||||
*
|
||||
* Description:
|
||||
* Set the ODMODE register for open drain mode
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC176x
|
||||
static void lpc17_setopendrain(unsigned int port, unsigned int pin)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
|
||||
regaddr = g_odmode[port];
|
||||
regval = getreg32(regaddr);
|
||||
regval |= (1 << pin);
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_clropendrain
|
||||
*
|
||||
* Description:
|
||||
* Reset the ODMODE register to disable open drain mode
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void lpc17_clropendrain(unsigned int port, unsigned int pin)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
|
||||
regaddr = g_odmode[port];
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~(1 << pin);
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
#endif /* LPC176x */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configinput
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO inpue pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t fiobase;
|
||||
uint32_t intbase;
|
||||
uint32_t pinmask = (1 << pin);
|
||||
|
||||
/* Set up FIO registers */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Set as input */
|
||||
|
||||
regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
regval &= ~pinmask;
|
||||
putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
|
||||
/* Set up interrupt registers */
|
||||
|
||||
intbase = g_intbase[port];
|
||||
if (intbase != 0)
|
||||
{
|
||||
/* Disable any rising edge interrupts */
|
||||
|
||||
regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
|
||||
regval &= ~pinmask;
|
||||
putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
|
||||
|
||||
/* Disable any falling edge interrupts */
|
||||
|
||||
regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
|
||||
regval &= ~pinmask;
|
||||
putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
|
||||
|
||||
/* Forget about any falling/rising edge interrupt enabled */
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc17_setintedge(port, pin, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set up PINSEL registers */
|
||||
/* Configure as GPIO */
|
||||
|
||||
#if defined(LPC176x)
|
||||
lpc17_pinsel(port, pin, PINCONN_PINSEL_GPIO);
|
||||
|
||||
/* Set pull-up mode */
|
||||
|
||||
lpc17_pullup(cfgset, port, pin);
|
||||
|
||||
/* Open drain only applies to outputs */
|
||||
|
||||
lpc17_clropendrain(port, pin);
|
||||
|
||||
#elif defined(LPC178x)
|
||||
/* Configure the pin as a GPIO. Clear opendrain, input inversion,
|
||||
* hysteris, slew. Set analog pins as digital.
|
||||
*/
|
||||
|
||||
regval = IOCON_FUNC_GPIO;
|
||||
|
||||
/* Set pull-up mode. Isolate the field from the cfgset and move it
|
||||
* into the correct position in the register value.
|
||||
*/
|
||||
|
||||
regval |= (((cfgset & GPIO_PUMODE_MASK) >> GPIO_PUMODE_SHIFT) << IOCON_MODE_SHIFT);
|
||||
|
||||
/* Select input polarity */
|
||||
|
||||
if ((cfgset & GPIO_INVERT) != 0)
|
||||
{
|
||||
regval |= IOCON_INV_MASK;
|
||||
}
|
||||
|
||||
/* Select hysteresis enable */
|
||||
|
||||
if ((cfgset & GPIO_HYSTERESIS) != 0)
|
||||
{
|
||||
regval |= IOCON_HYS_MASK;
|
||||
}
|
||||
|
||||
/* Set IOCON register */
|
||||
|
||||
lpc17_configiocon(port, pin, regval);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configinterrupt
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO interrupt pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin)
|
||||
{
|
||||
/* First, configure the port as a generic input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(cfgset, port, pin);
|
||||
|
||||
/* Then just remember the rising/falling edge interrupt enabled */
|
||||
|
||||
DEBUGASSERT(port == 0 || port == 2);
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configoutput
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO output pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
uint32_t regval;
|
||||
|
||||
/* First, configure the port as a generic input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
|
||||
|
||||
/* Now, reconfigure the pin as an output */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
regval |= (1 << pin);
|
||||
putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
|
||||
|
||||
#if defined(LPC176x)
|
||||
/* Check for open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
/* Set pull-up mode. This normally only applies to input pins, but does have
|
||||
* meaning if the port is an open drain output.
|
||||
*/
|
||||
|
||||
lpc17_pullup(cfgset, port, pin);
|
||||
|
||||
/* Select open drain output */
|
||||
|
||||
lpc17_setopendrain(port, pin);
|
||||
}
|
||||
|
||||
#elif defined(LPC178x)
|
||||
/* Configure the pin as a GPIO. Clear opendrain, input inversion,
|
||||
* hysteris, slew. Set analog pins as digital.
|
||||
*/
|
||||
|
||||
regval = IOCON_FUNC_GPIO;
|
||||
|
||||
/* Select open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
regval |= IOCON_OD_MASK;
|
||||
}
|
||||
|
||||
/* Select slew output */
|
||||
|
||||
if ((cfgset & GPIO_SLEW) != 0)
|
||||
{
|
||||
regval |= IOCON_SLEW_MASK;
|
||||
}
|
||||
|
||||
/* Set pull-up mode. Isolate the field from the cfgset and move it
|
||||
* into the correct position in the register value.
|
||||
*/
|
||||
|
||||
regval |= (((cfgset & GPIO_PUMODE_MASK) >> GPIO_PUMODE_SHIFT) << IOCON_MODE_SHIFT);
|
||||
|
||||
/* Set IOCON register */
|
||||
|
||||
lpc17_configiocon(port, pin, regval);
|
||||
#endif
|
||||
|
||||
/* Set the initial value of the output */
|
||||
|
||||
lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO));
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configalternate
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO alternate function pin based on bit-encoded description
|
||||
* of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
|
||||
unsigned int pin, uint32_t alt)
|
||||
{
|
||||
/* First, configure the port as an input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
|
||||
|
||||
#if defined(LPC176x)
|
||||
/* Set up PINSEL registers */
|
||||
/* Configure as GPIO */
|
||||
|
||||
lpc17_pinsel(port, pin, alt);
|
||||
|
||||
/* Set pull-up mode */
|
||||
|
||||
lpc17_pullup(cfgset, port, pin);
|
||||
|
||||
/* Check for open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
/* Select open drain output */
|
||||
|
||||
lpc17_setopendrain(port, pin);
|
||||
}
|
||||
|
||||
#elif defined(LPC178x)
|
||||
uint32_t regval = 0;
|
||||
|
||||
/* Select the alternate pin */
|
||||
|
||||
regval |= (alt & IOCON_FUNC_MASK);
|
||||
|
||||
/* Select analog mode */
|
||||
|
||||
if ((cfgset & GPIO_ADMODE) != 0)
|
||||
{
|
||||
regval |= IOCON_ADMODE_MASK;
|
||||
}
|
||||
|
||||
/* Set pull-up mode. Isolate the field from the cfgset and move it
|
||||
* into the correct position in the register value.
|
||||
*/
|
||||
|
||||
regval |= (((cfgset & GPIO_PUMODE_MASK) >> GPIO_PUMODE_SHIFT) << IOCON_MODE_SHIFT);
|
||||
|
||||
/* Select open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
regval |= IOCON_OD_MASK;
|
||||
}
|
||||
|
||||
/* Set IOCON register */
|
||||
|
||||
lpc17_configiocon(port, pin, regval);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc17_configgpio(lpc17_pinset_t cfgset)
|
||||
{
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
int ret = -EINVAL;
|
||||
|
||||
/* Verify that this hardware supports the select GPIO port */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the pin number and select the port configuration register for that pin */
|
||||
|
||||
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Handle according to pin function */
|
||||
|
||||
switch (cfgset & GPIO_FUNC_MASK)
|
||||
{
|
||||
case GPIO_INPUT: /* GPIO input pin */
|
||||
ret = lpc17_configinput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
ret = lpc17_configinterrupt(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT: /* GPIO outpout pin */
|
||||
ret = lpc17_configoutput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
#if defined(LPC176x)
|
||||
|
||||
case GPIO_ALT1: /* Alternate function 1 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2: /* Alternate function 2 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3: /* Alternate function 3 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3);
|
||||
break;
|
||||
|
||||
#elif defined(LPC178x)
|
||||
|
||||
case GPIO_ALT1: /* Alternate function 1 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2: /* Alternate function 2 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3: /* Alternate function 3 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3);
|
||||
break;
|
||||
|
||||
case GPIO_ALT4: /* Alternate function 4 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT4);
|
||||
break;
|
||||
|
||||
case GPIO_ALT5: /* Alternate function 5 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT5);
|
||||
break;
|
||||
|
||||
case GPIO_ALT6: /* Alternate function 6 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT6);
|
||||
break;
|
||||
|
||||
case GPIO_ALT7: /* Alternate function 7 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, IOCON_FUNC_ALT7);
|
||||
break;
|
||||
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
uint32_t offset;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
{
|
||||
offset = LPC17_FIO_SET_OFFSET;
|
||||
}
|
||||
else
|
||||
{
|
||||
offset = LPC17_FIO_CLR_OFFSET;
|
||||
}
|
||||
|
||||
putreg32((1 << pin), fiobase + offset);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool lpc17_gpioread(lpc17_pinset_t pinset)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -53,274 +53,23 @@
|
||||
#include "chip/lpc17_pinconn.h"
|
||||
#include "chip/lpc17_pinconfig.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Bit-encoded input to lpc17_configgpio() ******************************************/
|
||||
/* Include the GPIO definitions for the selected LPC17xx family. */
|
||||
|
||||
#if defined(LPC176x)
|
||||
|
||||
/* Encoding: FFFx MMOV PPPN NNNN
|
||||
*
|
||||
* Pin Function: FFF
|
||||
* Pin Mode bits: MM
|
||||
* Open drain: O (output pins)
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PPP (0-4)
|
||||
* Pin number: NNNNN (0-31)
|
||||
*/
|
||||
|
||||
/* Pin Function bits: FFF
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
|
||||
#define GPIO_FUNC_SHIFT (13) /* Bits 13-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT)
|
||||
#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0)
|
||||
|
||||
/* Pin Mode: MM */
|
||||
|
||||
#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
|
||||
# define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
|
||||
# define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
|
||||
# define GPIO_FLOAT (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
|
||||
# define GPIO_PULLDN (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
|
||||
|
||||
/* Open drain: O */
|
||||
|
||||
#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */
|
||||
|
||||
/* Initial value: V */
|
||||
|
||||
#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */
|
||||
#define GPIO_VALUE_ONE GPIO_VALUE
|
||||
#define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PPP (0-4) */
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_NPORTS 5
|
||||
|
||||
/* Pin number: NNNNN (0-31) */
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
# include "lpc176x_gpio.h"
|
||||
#elif defined(LPC178x)
|
||||
|
||||
/* Encoding: TTTT TTTT FFFF MMOV PPPN NNNN
|
||||
*
|
||||
* Special Pin Functions: TTTT TTTT
|
||||
* Pin Function: FFFF
|
||||
* Pin Mode bits: MM
|
||||
* Open drain: O (output pins)
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PPP (0-4)
|
||||
* Pin number: NNNNN (0-31)
|
||||
*/
|
||||
|
||||
/* Special Pin Functions
|
||||
* For pins that has ADC/DAC, USB, I2C
|
||||
*/
|
||||
|
||||
#define GPIO_IOCON_TYPE_D_MASK (0x0000067f) /* All port except where ADC/DAC, USB, I2C is present */
|
||||
#define GPIO_IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */
|
||||
#define GPIO_IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */
|
||||
#define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */
|
||||
#define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
|
||||
|
||||
#define GPIO_IOCON_MASK (0x00ff0000)
|
||||
# define GPIO_HYSTERESIS (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */
|
||||
# define GPIO_INVERT (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */
|
||||
# define GPIO_SLEW (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */
|
||||
# define GPIO_ADMODE (1 << 19) /* Bit 19: A/D Modes: 0-Analog, 1-Digital */
|
||||
# define GPIO_FILTER (1 << 20) /* Bit 20: Filter: 0-Off, 1-ON */
|
||||
# define GPIO_DACEN (1 << 21) /* Bit 21: DAC: 0-Disabled, 1-Enabled, P0:26 only */
|
||||
# define GPIO_I2CHS (1 << 22) /* Bit 22: Filter and Rate Control: 0-Enabled, 1-Disabled */
|
||||
# define GPIO_HIDRIVE (1 << 23) /* Bit 23: Current Sink: 0-4mA, 1-20mA P5:2 and P5:3 only,*/
|
||||
|
||||
/* Pin Function bits: FFFF
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
|
||||
#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO outpout pin */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */
|
||||
# define GPIO_ALT4 (8 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 4 */
|
||||
# define GPIO_ALT5 (9 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 5 */
|
||||
# define GPIO_ALT6 (10 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 6 */
|
||||
# define GPIO_ALT7 (11 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 7 */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (12) /* Bits 12-13: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT)
|
||||
#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0)
|
||||
|
||||
/* Pin Mode: MM */
|
||||
|
||||
#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
|
||||
# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
|
||||
# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
|
||||
# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
|
||||
# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
|
||||
|
||||
/* Open drain: O */
|
||||
|
||||
#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */
|
||||
|
||||
/* Initial value: V */
|
||||
|
||||
#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */
|
||||
# define GPIO_VALUE_ONE GPIO_VALUE
|
||||
# define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PPP (0-5) */
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_NPORTS 6
|
||||
|
||||
/* Pin number: NNNNN (0-31) */
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
# include "lpc178x_gpio.h"
|
||||
#else
|
||||
# error "Unrecognized LPC17xx family"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef LPC176x
|
||||
typedef uint16_t lpc17_pinset_t;
|
||||
#else
|
||||
typedef uint32_t lpc17_pinset_t;
|
||||
#endif
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
@ -347,14 +96,6 @@ EXTERN uint64_t g_intedge2;
|
||||
|
||||
EXTERN const uint32_t g_fiobase[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_intbase[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_lopinsel[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_hipinsel[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_lopinmode[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_hipinmode[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_odmode[GPIO_NPORTS];
|
||||
#ifdef LPC178x
|
||||
EXTERN const uint32_t g_ioconport[GPIO_NPORTS];
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user