sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

timer base name difference

Browse Source
This commit is contained in:
Lok Tep 2015-11-09 14:34:59 +01:00
parent 7d386866af
commit 1f8c0fdcdb
1 changed files with 68 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

136
arch/arm/src/lpc43xx/chip/lpc43_timer.h
View File

@ -68,77 +68,77 @@
/* Register addresses ***************************************************************/
#define LPC43_TMR0_IR (LPC43_TMR0_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR0_TCR (LPC43_TMR0_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR0_TC (LPC43_TMR0_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR0_PR (LPC43_TMR0_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR0_PC (LPC43_TMR0_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR0_MCR (LPC43_TMR0_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR0_MR0 (LPC43_TMR0_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR0_MR1 (LPC43_TMR0_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR0_MR2 (LPC43_TMR0_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR0_MR3 (LPC43_TMR0_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR0_CCR (LPC43_TMR0_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR0_CR0 (LPC43_TMR0_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR0_CR1 (LPC43_TMR0_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR0_CR2 (LPC43_TMR0_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR0_CR3 (LPC43_TMR0_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR0_EMR (LPC43_TMR0_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR0_CTCR (LPC43_TMR0_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR0_IR (LPC43_TIMER0_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR0_TCR (LPC43_TIMER0_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR0_TC (LPC43_TIMER0_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR0_PR (LPC43_TIMER0_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR0_PC (LPC43_TIMER0_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR0_MCR (LPC43_TIMER0_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR0_MR0 (LPC43_TIMER0_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR0_MR1 (LPC43_TIMER0_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR0_MR2 (LPC43_TIMER0_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR0_MR3 (LPC43_TIMER0_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR0_CCR (LPC43_TIMER0_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR0_CR0 (LPC43_TIMER0_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR0_CR1 (LPC43_TIMER0_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR0_CR2 (LPC43_TIMER0_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR0_CR3 (LPC43_TIMER0_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR0_EMR (LPC43_TIMER0_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR0_CTCR (LPC43_TIMER0_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR1_IR (LPC43_TMR1_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR1_TCR (LPC43_TMR1_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR1_TC (LPC43_TMR1_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR1_PR (LPC43_TMR1_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR1_PC (LPC43_TMR1_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR1_MCR (LPC43_TMR1_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR1_MR0 (LPC43_TMR1_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR1_MR1 (LPC43_TMR1_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR1_MR2 (LPC43_TMR1_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR1_MR3 (LPC43_TMR1_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR1_CCR (LPC43_TMR1_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR1_CR0 (LPC43_TMR1_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR1_CR1 (LPC43_TMR1_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR1_CR2 (LPC43_TMR1_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR1_CR3 (LPC43_TMR1_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR1_EMR (LPC43_TMR1_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR1_CTCR (LPC43_TMR1_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR1_IR (LPC43_TIMER1_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR1_TCR (LPC43_TIMER1_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR1_TC (LPC43_TIMER1_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR1_PR (LPC43_TIMER1_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR1_PC (LPC43_TIMER1_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR1_MCR (LPC43_TIMER1_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR1_MR0 (LPC43_TIMER1_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR1_MR1 (LPC43_TIMER1_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR1_MR2 (LPC43_TIMER1_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR1_MR3 (LPC43_TIMER1_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR1_CCR (LPC43_TIMER1_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR1_CR0 (LPC43_TIMER1_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR1_CR1 (LPC43_TIMER1_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR1_CR2 (LPC43_TIMER1_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR1_CR3 (LPC43_TIMER1_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR1_EMR (LPC43_TIMER1_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR1_CTCR (LPC43_TIMER1_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR2_IR (LPC43_TMR2_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR2_TCR (LPC43_TMR2_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR2_TC (LPC43_TMR2_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR2_PR (LPC43_TMR2_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR2_PC (LPC43_TMR2_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR2_MCR (LPC43_TMR2_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR2_MR0 (LPC43_TMR2_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR2_MR1 (LPC43_TMR2_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR2_MR2 (LPC43_TMR2_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR2_MR3 (LPC43_TMR2_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR2_CCR (LPC43_TMR2_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR2_CR0 (LPC43_TMR2_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR2_CR1 (LPC43_TMR2_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR2_CR2 (LPC43_TMR2_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR2_CR3 (LPC43_TMR2_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR2_EMR (LPC43_TMR2_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR2_CTCR (LPC43_TMR2_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR2_IR (LPC43_TIMER2_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR2_TCR (LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR2_TC (LPC43_TIMER2_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR2_PR (LPC43_TIMER2_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR2_PC (LPC43_TIMER2_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR2_MCR (LPC43_TIMER2_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR2_MR0 (LPC43_TIMER2_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR2_MR1 (LPC43_TIMER2_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR2_MR2 (LPC43_TIMER2_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR2_MR3 (LPC43_TIMER2_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR2_CCR (LPC43_TIMER2_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR2_CR0 (LPC43_TIMER2_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR2_CR1 (LPC43_TIMER2_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR2_CR2 (LPC43_TIMER2_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR2_CR3 (LPC43_TIMER2_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR2_EMR (LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR2_CTCR (LPC43_TIMER2_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR3_IR (LPC43_TMR3_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR3_TCR (LPC43_TMR3_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR3_TC (LPC43_TMR3_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR3_PR (LPC43_TMR3_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR3_PC (LPC43_TMR3_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR3_MCR (LPC43_TMR3_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR3_MR0 (LPC43_TMR3_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR3_MR1 (LPC43_TMR3_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR3_MR2 (LPC43_TMR3_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR3_MR3 (LPC43_TMR3_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR3_CCR (LPC43_TMR3_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR3_CR0 (LPC43_TMR3_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR3_CR1 (LPC43_TMR3_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR3_CR2 (LPC43_TMR3_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR3_CR3 (LPC43_TMR3_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR3_EMR (LPC43_TMR3_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR3_CTCR (LPC43_TMR3_BASE+LPC43_TMR_CTCR_OFFSET)
#define LPC43_TMR3_IR (LPC43_TIMER3_BASE+LPC43_TMR_IR_OFFSET)
#define LPC43_TMR3_TCR (LPC43_TIMER3_BASE+LPC43_TMR_TCR_OFFSET)
#define LPC43_TMR3_TC (LPC43_TIMER3_BASE+LPC43_TMR_TC_OFFSET)
#define LPC43_TMR3_PR (LPC43_TIMER3_BASE+LPC43_TMR_PR_OFFSET)
#define LPC43_TMR3_PC (LPC43_TIMER3_BASE+LPC43_TMR_PC_OFFSET)
#define LPC43_TMR3_MCR (LPC43_TIMER3_BASE+LPC43_TMR_MCR_OFFSET)
#define LPC43_TMR3_MR0 (LPC43_TIMER3_BASE+LPC43_TMR_MR0_OFFSET)
#define LPC43_TMR3_MR1 (LPC43_TIMER3_BASE+LPC43_TMR_MR1_OFFSET)
#define LPC43_TMR3_MR2 (LPC43_TIMER3_BASE+LPC43_TMR_MR2_OFFSET)
#define LPC43_TMR3_MR3 (LPC43_TIMER3_BASE+LPC43_TMR_MR3_OFFSET)
#define LPC43_TMR3_CCR (LPC43_TIMER3_BASE+LPC43_TMR_CCR_OFFSET)
#define LPC43_TMR3_CR0 (LPC43_TIMER3_BASE+LPC43_TMR_CR0_OFFSET)
#define LPC43_TMR3_CR1 (LPC43_TIMER3_BASE+LPC43_TMR_CR1_OFFSET)
#define LPC43_TMR3_CR2 (LPC43_TIMER3_BASE+LPC43_TMR_CR2_OFFSET)
#define LPC43_TMR3_CR3 (LPC43_TIMER3_BASE+LPC43_TMR_CR3_OFFSET)
#define LPC43_TMR3_EMR (LPC43_TIMER3_BASE+LPC43_TMR_EMR_OFFSET)
#define LPC43_TMR3_CTCR (LPC43_TIMER3_BASE+LPC43_TMR_CTCR_OFFSET)
/* Register bit definitions *********************************************************/
/* Registers holding 32-bit numeric values (no bit field definitions):