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Tiva: Fix some cosmetic spacing issues

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This commit is contained in:
Gregory Nutt 2015-10-07 15:57:49 -06:00
parent 4f2119b3f4
commit 20d87b38de
18 changed files with 214 additions and 197 deletions
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21
arch/arm/src/tiva/lm3s_ethernet.c
View File

@ -189,7 +189,7 @@ struct tiva_statistics_s
uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */
uint32_t tx_int; /* Number of Tx interrupts received */
uint32_t tx_packets; /* Number of Tx packets queued */
uint32_t tx_errors; /* Number of Tx errors (transmission error)*/
uint32_t tx_errors; /* Number of Tx errors (transmission error) */
uint32_t tx_timeouts; /* Number of Tx timeout errors */
};
# define EMAC_STAT(priv,name) priv->ld_stat.name++
@ -364,14 +364,14 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
flags = irqsave();
regval = getreg32(TIVA_SYSCON_RCGC2);
regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
regval |= (SYSCON_RCGC2_EMAC0 | SYSCON_RCGC2_EPHY0);
putreg32(regval, TIVA_SYSCON_RCGC2);
nllvdbg("RCGC2: %08x\n", regval);
/* Put the Ethernet controller into the reset state */
regval = getreg32(TIVA_SYSCON_SRCR2);
regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
regval |= (SYSCON_SRCR2_EMAC0 | SYSCON_SRCR2_EPHY0);
putreg32(regval, TIVA_SYSCON_SRCR2);
/* Wait just a bit. This is a much longer delay than necessary */
@ -380,7 +380,7 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
/* Then take the Ethernet controller out of the reset state */
regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
regval &= ~(SYSCON_SRCR2_EMAC0 | SYSCON_SRCR2_EPHY0);
putreg32(regval, TIVA_SYSCON_SRCR2);
nllvdbg("SRCR2: %08x\n", regval);
@ -545,7 +545,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
* buffer may be un-aligned.
*/
tiva_ethout(priv, TIVA_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
tiva_ethout(priv, TIVA_MAC_DATA_OFFSET, *(uint32_t *)dbuf);
}
/* Write the last, partial word in the FIFO */
@ -756,7 +756,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
* buffer may be un-aligned.
*/
*(uint32_t*)dbuf = tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
*(uint32_t *)dbuf = tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
}
/* Handle the last, partial word in the FIFO (0-3 bytes) and discard
@ -1135,7 +1135,7 @@ static int tiva_ifup(struct net_driver_s *dev)
nlldbg("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Enable and reset the Ethernet controller */
@ -1289,7 +1289,7 @@ static int tiva_ifdown(struct net_driver_s *dev)
nlldbg("Taking down: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Cancel the TX poll timer and TX timeout timers */
@ -1489,7 +1489,8 @@ static inline int tiva_ethinitialize(int intf)
#if TIVA_NETHCONTROLLERS > 1
# error "This debug check only works with one interface"
#else
DEBUGASSERT((getreg32(TIVA_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
DEBUGASSERT((getreg32(TIVA_SYSCON_DC4) & (SYSCON_DC4_EMAC0 | SYSCON_DC4_EPHY0)) ==
(SYSCON_DC4_EMAC0 | SYSCON_DC4_EPHY0));
#endif
DEBUGASSERT((unsigned)intf < TIVA_NETHCONTROLLERS);
@ -1503,7 +1504,7 @@ static inline int tiva_ethinitialize(int intf)
priv->ld_dev.d_addmac = tiva_addmac; /* Add multicast MAC address */
priv->ld_dev.d_rmmac = tiva_rmmac; /* Remove multicast MAC address */
#endif
priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */
priv->ld_dev.d_private = (void *)priv; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */

8
arch/arm/src/tiva/tiva_adclib.c
View File

@ -77,8 +77,8 @@
****************************************************************************/
#define CLOCK_CONFIG(div, src) \
( ((((div) << ADC_CC_CLKDIV_SHIFT) & ADC_CC_CLKDIV_MASK) | \
((src) & ADC_CC_CS_MASK)) & (ADC_CC_CLKDIV_MASK + ADC_CC_CS_MASK) )
(((((div) << ADC_CC_CLKDIV_SHIFT) & ADC_CC_CLKDIV_MASK) | \
((src) & ADC_CC_CS_MASK)) & (ADC_CC_CLKDIV_MASK + ADC_CC_CS_MASK))
/****************************************************************************
* Private Types
@ -259,7 +259,7 @@ void tiva_adc_configure(struct tiva_adc_cfg_s *cfg)
/* Configure each SSE */
for (s=0; s<4; ++s)
for (s = 0; s < 4; ++s)
{
if (cfg->sse[s])
{
@ -275,7 +275,7 @@ void tiva_adc_configure(struct tiva_adc_cfg_s *cfg)
/* Configure each step */
for (c=0; c<cfg->steps; ++c)
for (c = 0; c < cfg->steps; ++c)
{
tiva_adc_step_cfg(&cfg->stepcfg[c]);
}

56
arch/arm/src/tiva/tiva_adclow.c
View File

@ -116,7 +116,7 @@
*/
#define ADC_TRIG_PWM_CFG(t) \
(1<<(ADC_TSSEL_PS_SHIFT(ADC_TRIG_gen(t))))
(1 << (ADC_TSSEL_PS_SHIFT(ADC_TRIG_gen(t))))
/* ADC support definitions **************************************************/
@ -466,7 +466,7 @@ static void tiva_adc_shutdown(struct adc_dev_s *dev)
struct tiva_adc_sse_s *sse;
uint8_t s = 0;
for (s=0; s<4; ++s)
for (s = 0; s < 4; ++s)
{
}
#endif
@ -496,7 +496,7 @@ static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable)
DEBUGASSERT(priv->ena);
for (s=0; s<4; ++s)
for (s = 0; s < 4; ++s)
{
trigger = tiva_adc_get_trigger(priv->devno, s);
sse = g_sses[SSE_IDX(priv->devno, s)];
@ -559,7 +559,7 @@ static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
fifo_count = tiva_adc_sse_data(priv->devno, sse, buf);
for (i=0; i<fifo_count; ++i)
for (i = 0; i < fifo_count; ++i)
{
(void)adc_receive(dev,
tiva_adc_get_ain(priv->devno, sse, i),
@ -656,7 +656,7 @@ static void tiva_adc_read(void *arg)
return;
}
for (i=0; i<fifo_count; ++i)
for (i = 0; i < fifo_count; ++i)
{
(void)adc_receive(dev,
tiva_adc_get_ain(sse->adc, sse->num, i),
@ -743,7 +743,7 @@ static struct tiva_adc_s *tiva_adc_struct_init(struct tiva_adc_cfg_s *cfg)
adc->ena = false;
adc->devno = cfg->adc;
for (s=0; s<4; s++)
for (s = 0; s < 4; s++)
{
/* Only configure selected SSEs */
@ -903,7 +903,7 @@ void tiva_adc_lock(FAR struct tiva_adc_s *priv, int sse)
struct tiva_adc_sse_s *s = g_sses[SSE_IDX(priv->devno, sse)];
int ret;
#ifdef CONFIG_DEBUG_ANALOG
uint16_t loop_count=0;
uint16_t loop_count = 0;
#endif
do
@ -958,21 +958,33 @@ static void tiva_adc_runtimeobj_ptrs(void)
{
# ifdef CONFIG_TIVA_ADC0
avdbg("ADC0 [struct] [global value] [array value]\n");
avdbg(" adc_dev_s dev0=0x%08x g_devs[0]=0x%08x\n", &dev0, g_devs[0]);
avdbg(" tiva_adc_s adc0=0x%08x g_adcs[0]=0x%08x\n", &adc0, g_adcs[0]);
avdbg(" tiva_adc_sse_s sse0=0x%08x g_sses[0,0]=0x%08x\n", &sse00, g_sses[SSE_IDX(0,0)]);
avdbg(" tiva_adc_sse_s sse1=0x%08x g_sses[0,1]=0x%08x\n", &sse01, g_sses[SSE_IDX(0,1)]);
avdbg(" tiva_adc_sse_s sse2=0x%08x g_sses[0,2]=0x%08x\n", &sse02, g_sses[SSE_IDX(0,2)]);
avdbg(" tiva_adc_sse_s sse3=0x%08x g_sses[0,3]=0x%08x\n", &sse03, g_sses[SSE_IDX(0,3)]);
avdbg(" adc_dev_s dev0=0x%08x g_devs[0]=0x%08x\n",
&dev0, g_devs[0]);
avdbg(" tiva_adc_s adc0=0x%08x g_adcs[0]=0x%08x\n",
&adc0, g_adcs[0]);
avdbg(" tiva_adc_sse_s sse0=0x%08x g_sses[0,0]=0x%08x\n",
&sse00, g_sses[SSE_IDX(0, 0)]);
avdbg(" tiva_adc_sse_s sse1=0x%08x g_sses[0,1]=0x%08x\n",
&sse01, g_sses[SSE_IDX(0, 1)]);
avdbg(" tiva_adc_sse_s sse2=0x%08x g_sses[0,2]=0x%08x\n",
&sse02, g_sses[SSE_IDX(0, 2)]);
avdbg(" tiva_adc_sse_s sse3=0x%08x g_sses[0,3]=0x%08x\n",
&sse03, g_sses[SSE_IDX(0, 3)]);
# endif
# ifdef CONFIG_TIVA_ADC1
avdbg("ADC1 [struct] [global value] [array value]\n");
avdbg(" adc_dev_s dev1=0x%08x g_devs[1]=0x%08x\n", &dev1, g_devs[1]);
avdbg(" tiva_adc_s adc1=0x%08x g_adcs[1]=0x%08x\n", &adc1, g_adcs[1]);
avdbg(" tiva_adc_sse_s sse0=0x%08x g_sses[1,0]=0x%08x\n", &sse10, g_sses[SSE_IDX(1,0)]);
avdbg(" tiva_adc_sse_s sse1=0x%08x g_sses[1,1]=0x%08x\n", &sse11, g_sses[SSE_IDX(1,1)]);
avdbg(" tiva_adc_sse_s sse2=0x%08x g_sses[1,2]=0x%08x\n", &sse12, g_sses[SSE_IDX(1,2)]);
avdbg(" tiva_adc_sse_s sse3=0x%08x g_sses[1,3]=0x%08x\n", &sse13, g_sses[SSE_IDX(1,3)]);
avdbg(" adc_dev_s dev1=0x%08x g_devs[1]=0x%08x\n",
&dev1, g_devs[1]);
avdbg(" tiva_adc_s adc1=0x%08x g_adcs[1]=0x%08x\n",
&adc1, g_adcs[1]);
avdbg(" tiva_adc_sse_s sse0=0x%08x g_sses[1,0]=0x%08x\n",
&sse10, g_sses[SSE_IDX(1, 0)]);
avdbg(" tiva_adc_sse_s sse1=0x%08x g_sses[1,1]=0x%08x\n",
&sse11, g_sses[SSE_IDX(1, 1)]);
avdbg(" tiva_adc_sse_s sse2=0x%08x g_sses[1,2]=0x%08x\n",
&sse12, g_sses[SSE_IDX(1, 2)]);
avdbg(" tiva_adc_sse_s sse3=0x%08x g_sses[1,3]=0x%08x\n",
&sse13, g_sses[SSE_IDX(1, 3)]);
# endif
}
@ -983,7 +995,8 @@ static void tiva_adc_runtimeobj_vals(void)
# ifdef CONFIG_TIVA_ADC0
avdbg("ADC0 [0x%08x] cfg=%d ena=%d devno=%d\n",
&adc0, adc0.cfg, adc0.ena, adc0.devno);
for (s=0; s<4; ++s)
for (s = 0; s < 4; ++s)
{
sse = g_sses[SSE_IDX(0, s)];
avdbg("SSE%d [0x%08x] adc=%d cfg=%d ena=%d num=%d\n",
@ -993,7 +1006,8 @@ static void tiva_adc_runtimeobj_vals(void)
# ifdef CONFIG_TIVA_ADC1
avdbg("ADC1 [0x%08x] cfg=%d ena=%d devno=%d\n",
&adc1, adc1.cfg, adc1.ena, adc1.devno);
for (s=0; s<4; ++s)
for (s = 0; s < 4; ++s)
{
sse = g_sses[SSE_IDX(1, s)];
avdbg("SSE%d [0x%08x] adc=%d cfg=%d ena=%d num=%d\n",

6
arch/arm/src/tiva/tiva_allocateheap.c
View File

@ -132,7 +132,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Allow user-mode access to the user heap memory */
@ -143,7 +143,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
}
@ -187,7 +187,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void*)USERSPACE->us_bssend;
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif

4
arch/arm/src/tiva/tiva_dumpgpio.c
View File

@ -170,10 +170,10 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
tiva_gpioport(port), pinset, base, msg);
#ifdef TIVA_SYSCON_RCGCGPIO
lldbg("RCGCGPIO: %08x (%s)\n",
rcgcgpio, enabled ? "enabled" : "disabled" );
rcgcgpio, enabled ? "enabled" : "disabled");
#else
lldbg(" RCGC2: %08x (%s)\n",
rcgc2, enabled ? "enabled" : "disabled" );
rcgc2, enabled ? "enabled" : "disabled");
#endif
/* Don't bother with the rest unless the port is enabled */

10
arch/arm/src/tiva/tiva_flash.c
View File

@ -178,7 +178,7 @@ static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nb
{
DEBUGASSERT(startblock + nblocks <= TIVA_VIRTUAL_NPAGES);
memcpy(buf, (void*)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE),
memcpy(buf, (void *)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE),
nblocks * TIVA_FLASH_PAGESIZE);
return nblocks;
@ -195,8 +195,8 @@ static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nb
static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR const uint8_t *buf)
{
FAR uint32_t *src = (uint32_t*)buf;
FAR uint32_t *dst = (uint32_t*)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE);
FAR uint32_t *src = (uint32_t *)buf;
FAR uint32_t *dst = (uint32_t *)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE);
int i;
DEBUGASSERT(nblocks <= TIVA_VIRTUAL_NPAGES);
@ -236,7 +236,7 @@ static ssize_t tiva_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
{
DEBUGASSERT(offset + nbytes < TIVA_VIRTUAL_NPAGES * TIVA_FLASH_PAGESIZE);
memcpy(buf, (void*)(TIVA_VIRTUAL_BASE + offset), nbytes);
memcpy(buf, (void *)(TIVA_VIRTUAL_BASE + offset), nbytes);
return nbytes;
}
@ -301,7 +301,7 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
* this case altogether and simply return -ENOTTY.
*/
*ppv = (void*)TIVA_VIRTUAL_BASE;
*ppv = (void *)TIVA_VIRTUAL_BASE;
ret = OK;
}
}

2
arch/arm/src/tiva/tiva_gpio.c
View File

@ -506,7 +506,7 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
/* Set the pin type. */
switch(padtype)
switch (padtype)
{
case GPIO_PADTYPE_STD:
{

6
arch/arm/src/tiva/tiva_irq.c
View File

@ -61,9 +61,9 @@
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
NVIC_SYSH_PRIORITY_DEFAULT << 8 |\
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to

18
arch/arm/src/tiva/tiva_lowputc.c
View File

@ -237,11 +237,11 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait until the TX FIFO is not full */
while ((getreg32(TIVA_CONSOLE_BASE+TIVA_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
while ((getreg32(TIVA_CONSOLE_BASE + TIVA_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
/* Then send the character */
putreg32((uint32_t)ch, TIVA_CONSOLE_BASE+TIVA_UART_DR_OFFSET);
putreg32((uint32_t)ch, TIVA_CONSOLE_BASE + TIVA_UART_DR_OFFSET);
#endif
}
@ -351,25 +351,25 @@ void up_lowsetup(void)
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
ctl = getreg32(TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
ctl = getreg32(TIVA_CONSOLE_BASE + TIVA_UART_CTL_OFFSET);
ctl &= ~UART_CTL_UARTEN;
putreg32(ctl, TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
putreg32(ctl, TIVA_CONSOLE_BASE + TIVA_UART_CTL_OFFSET);
/* Write the integer portion of the BRD to the UART IBRD register */
putreg32(TIVA_BRDI, TIVA_CONSOLE_BASE+TIVA_UART_IBRD_OFFSET);
putreg32(TIVA_BRDI, TIVA_CONSOLE_BASE + TIVA_UART_IBRD_OFFSET);
/* Write the fractional portion of the BRD to the UART FBRD register */
putreg32(TIVA_DIVFRAC, TIVA_CONSOLE_BASE+TIVA_UART_FBRD_OFFSET);
putreg32(TIVA_DIVFRAC, TIVA_CONSOLE_BASE + TIVA_UART_FBRD_OFFSET);
/* Write the desired serial parameters to the UART LCRH register */
putreg32(UART_LCRH_VALUE, TIVA_CONSOLE_BASE+TIVA_UART_LCRH_OFFSET);
putreg32(UART_LCRH_VALUE, TIVA_CONSOLE_BASE + TIVA_UART_LCRH_OFFSET);
/* Enable the UART by setting the UARTEN bit in the UART CTL register */
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
putreg32(ctl, TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
ctl |= (UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
putreg32(ctl, TIVA_CONSOLE_BASE + TIVA_UART_CTL_OFFSET);
#endif
}

47
arch/arm/src/tiva/tiva_serial.c
View File

@ -719,7 +719,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv)
static int up_setup(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t lcrh;
uint32_t ctl;
#ifndef CONFIG_SUPPRESS_UART_CONFIG
@ -812,7 +812,7 @@ static int up_setup(struct uart_dev_s *dev)
lcrh |= UART_LCRH_PEN;
break;
case 2:
lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
lcrh |= UART_LCRH_PEN | UART_LCRH_EPS;
break;
}
@ -828,9 +828,10 @@ static int up_setup(struct uart_dev_s *dev)
* any character is received.
*/
up_serialout(priv, TIVA_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
up_serialout(priv, TIVA_UART_IFLS_OFFSET,
UART_IFLS_TXIFLSEL_18th | UART_IFLS_RXIFLSEL_18th);
/* Flush the Rx and Tx FIFOs -- How do you do that?*/
/* Flush the Rx and Tx FIFOs -- How do you do that? */
/* Enable Rx interrupts from the UART except for Tx interrupts. We don't want
* Tx interrupts until we have something to send. We will check for serial
@ -838,7 +839,7 @@ static int up_setup(struct uart_dev_s *dev)
* yet because the interrupt is still disabled at the interrupt controller.
*/
up_serialout(priv, TIVA_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
up_serialout(priv, TIVA_UART_IM_OFFSET, UART_IM_RXIM | UART_IM_RTIM);
/* Enable the FIFOs */
@ -853,7 +854,7 @@ static int up_setup(struct uart_dev_s *dev)
#ifdef CONFIG_SUPPRESS_UART_CONFIG
ctl = up_serialin(priv, TIVA_UART_CTL_OFFSET);
#endif
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
ctl |= (UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
up_serialout(priv, TIVA_UART_CTL_OFFSET, ctl);
/* Set up the cache IM value */
@ -873,7 +874,7 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disableuartint(priv, NULL);
}
@ -894,7 +895,7 @@ static void up_shutdown(struct uart_dev_s *dev)
static int up_attach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int ret;
/* Attach and enable the IRQ */
@ -908,6 +909,7 @@ static int up_attach(struct uart_dev_s *dev)
up_enable_irq(priv->irq);
}
return ret;
}
@ -923,7 +925,7 @@ static int up_attach(struct uart_dev_s *dev)
static void up_detach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disable_irq(priv->irq);
irq_detach(priv->irq);
}
@ -1009,7 +1011,7 @@ static int up_interrupt(int irq, void *context)
PANIC();
}
priv = (struct up_dev_s*)dev->priv;
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
* until we have been looping for a long time.
@ -1027,7 +1029,7 @@ static int up_interrupt(int irq, void *context)
/* Handle incoming, receive bytes (with or without timeout) */
if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
if ((mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) != 0)
{
/* Rx buffer not empty ... process incoming bytes */
@ -1045,6 +1047,7 @@ static int up_interrupt(int irq, void *context)
handled = true;
}
}
return OK;
}
@ -1069,7 +1072,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
case TIOCSERGSTRUCT:
{
struct up_dev_s *user = (struct up_dev_s*)arg;
struct up_dev_s *user = (struct up_dev_s *)arg;
if (!user)
{
ret = -EINVAL;
@ -1102,7 +1105,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rxd;
/* Get the Rx byte + 4 bits of error information. Return those in status */
@ -1125,7 +1128,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
if (enable)
{
/* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
@ -1133,12 +1136,12 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
*/
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
priv->im |= (UART_IM_RXIM | UART_IM_RTIM);
#endif
}
else
{
priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
priv->im &= ~(UART_IM_RXIM | UART_IM_RTIM);
}
up_serialout(priv, TIVA_UART_IM_OFFSET, priv->im);
}
@ -1153,7 +1156,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
}
@ -1167,7 +1170,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_serialout(priv, TIVA_UART_DR_OFFSET, (uint32_t)ch);
}
@ -1181,7 +1184,7 @@ static void up_send(struct uart_dev_s *dev, int ch)
static void up_txint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
irqstate_t flags;
flags = irqsave();
@ -1226,7 +1229,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
}
@ -1240,7 +1243,7 @@ static bool up_txready(struct uart_dev_s *dev)
static bool up_txempty(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
}
@ -1351,7 +1354,7 @@ void up_serialinit(void)
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
uint32_t im;
up_disableuartint(priv, &im);

38
arch/arm/src/tiva/tiva_ssi.c
View File

@ -548,18 +548,18 @@ static void ssi_txnull(struct tiva_ssidev_s *priv)
static void ssi_txuint16(struct tiva_ssidev_s *priv)
{
uint16_t *ptr = (uint16_t*)priv->txbuffer;
uint16_t *ptr = (uint16_t *)priv->txbuffer;
ssivdbg("TX: %p->%04x\n", ptr, *ptr);
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, (uint32_t)(*ptr++));
priv->txbuffer = (void*)ptr;
priv->txbuffer = (void *)ptr;
}
static void ssi_txuint8(struct tiva_ssidev_s *priv)
{
uint8_t *ptr = (uint8_t*)priv->txbuffer;
uint8_t *ptr = (uint8_t *)priv->txbuffer;
ssivdbg("TX: %p->%02x\n", ptr, *ptr);
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, (uint32_t)(*ptr++));
priv->txbuffer = (void*)ptr;
priv->txbuffer = (void *)ptr;
}
/****************************************************************************
@ -591,18 +591,18 @@ static void ssi_rxnull(struct tiva_ssidev_s *priv)
static void ssi_rxuint16(struct tiva_ssidev_s *priv)
{
uint16_t *ptr = (uint16_t*)priv->rxbuffer;
uint16_t *ptr = (uint16_t *)priv->rxbuffer;
*ptr = (uint16_t)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
priv->rxbuffer = (void*)(++ptr);
priv->rxbuffer = (void *)(++ptr);
}
static void ssi_rxuint8(struct tiva_ssidev_s *priv)
{
uint8_t *ptr = (uint8_t*)priv->rxbuffer;
uint8_t *ptr = (uint8_t *)priv->rxbuffer;
*ptr = (uint8_t)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
priv->rxbuffer = (void*)(++ptr);
priv->rxbuffer = (void *)(++ptr);
}
/****************************************************************************
@ -724,7 +724,7 @@ static int ssi_performtx(struct tiva_ssidev_s *priv)
*/
#ifdef CONFIG_DEBUG
regval |= (SSI_IM_TX|SSI_RIS_ROR);
regval |= (SSI_IM_TX | SSI_RIS_ROR);
#else
regval |= SSI_IM_TX;
#endif
@ -735,7 +735,7 @@ static int ssi_performtx(struct tiva_ssidev_s *priv)
* the transfer will be driven by Rx FIFO interrupts.
*/
regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
regval &= ~(SSI_IM_TX | SSI_RIS_ROR);
}
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, regval);
#endif /* CONFIG_SSI_POLLWAIT */
@ -797,9 +797,9 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv)
*/
#ifdef CONFIG_DEBUG
regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR);
regval |= (SSI_IM_RX | SSI_IM_RT | SSI_IM_ROR);
#else
regval |= (SSI_IM_RX|SSI_IM_RT);
regval |= (SSI_IM_RX | SSI_IM_RT);
#endif
}
else
@ -808,7 +808,7 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv)
* have received. Disable Rx FIFO interrupts.
*/
regval &= ~(SSI_IM_RX|SSI_IM_RT);
regval &= ~(SSI_IM_RX | SSI_IM_RT);
}
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, regval);
#endif /* CONFIG_SSI_POLLWAIT */
@ -849,8 +849,8 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
/* Set up to perform the transfer */
priv->txbuffer = (uint8_t*)txbuffer; /* Source buffer */
priv->rxbuffer = (uint8_t*)rxbuffer; /* Destination buffer */
priv->txbuffer = (uint8_t *)txbuffer; /* Source buffer */
priv->rxbuffer = (uint8_t *)rxbuffer; /* Destination buffer */
priv->ntxwords = nwords; /* Number of words left to send */
priv->nrxwords = 0; /* Number of words received */
priv->nwords = nwords; /* Total number of exchanges */
@ -1300,7 +1300,7 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, enum spi_mode_e mode
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
modebits = SSI_CR0_SPH|SSI_CR0_SPO;
modebits = SSI_CR0_SPH | SSI_CR0_SPO;
break;
default:
@ -1310,7 +1310,7 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, enum spi_mode_e mode
/* Then set the selected mode: Freescale SPI format, mode0-3 */
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
regval &= ~(SSI_CR0_FRF_MASK | SSI_CR0_SPH | SSI_CR0_SPO);
regval |= modebits;
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x\n", regval);
@ -1359,7 +1359,7 @@ static void ssi_setbitsinternal(struct tiva_ssidev_s *priv, int nbits)
ssidbg("nbits: %d\n", nbits);
DEBUGASSERT(priv);
if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
if (nbits != priv->nbits && nbits >= 4 && nbits <= 16)
{
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
regval &= ~SSI_CR0_DSS_MASK;
@ -1401,7 +1401,7 @@ static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits)
static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd)
{
struct tiva_ssidev_s *priv = (struct tiva_ssidev_s*)dev;
struct tiva_ssidev_s *priv = (struct tiva_ssidev_s *)dev;
uint16_t response = 0;
(void)ssi_transfer(priv, &wd, &response, 1);

2
arch/arm/src/tiva/tiva_start.c
View File

@ -168,5 +168,5 @@ void __start(void)
/* Shouldn't get here */
for (;;);
for (; ; );
}

2
arch/arm/src/tiva/tiva_syscontrol.c
View File

@ -319,13 +319,11 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
}
}
#elif defined(CONFIG_ARCH_CHIP_CC3200)
{
#if 0
/* NOTE: we do this in up_earlyconsoleinit() */
cc3200_init();
#endif
}
#else
if (((rcc & SYSCON_RCC_MOSCDIS) != 0 && (newrcc & SYSCON_RCC_MOSCDIS) == 0) ||
((rcc & SYSCON_RCC_IOSCDIS) != 0 && (newrcc & SYSCON_RCC_IOSCDIS) == 0))

3
arch/arm/src/tiva/tiva_timerisr.c
View File

@ -134,7 +134,8 @@ void up_timer_initialize(void)
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */

10
arch/arm/src/tiva/tiva_userspace.c
View File

@ -87,8 +87,8 @@ void tiva_userspace(void)
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t*)USERSPACE->us_bssstart;
end = (uint8_t*)USERSPACE->us_bssend;
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
@ -101,9 +101,9 @@ void tiva_userspace(void)
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t*)USERSPACE->us_datasource;
dest = (uint8_t*)USERSPACE->us_datastart;
end = (uint8_t*)USERSPACE->us_dataend;
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{

20
arch/arm/src/tiva/tm4c_ethernet.c
View File

@ -513,7 +513,7 @@
(EMAC_DMABUSMOD_SWR | EMAC_DMABUSMOD_DA | EMAC_DMABUSMOD_DSL_MASK | \
EMAC_DMABUSMOD_ATDS | EMAC_DMABUSMOD_PBL_MASK | EMAC_DMABUSMOD_PR_MASK | \
EMAC_DMABUSMOD_FB | EMAC_DMABUSMOD_RPBL_MASK | EMAC_DMABUSMOD_USP | \
EMAC_DMABUSMOD_8XPBL | EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_MB |\
EMAC_DMABUSMOD_8XPBL | EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_MB | \
EMAC_DMABUSMOD_TXPR | EMAC_DMABUSMOD_RIB)
/* The following bits are set or left zero unconditionally in all modes.
@ -583,7 +583,7 @@
*/
#define EMAC_DMAINT_NORMAL \
(EMAC_DMAINT_TI | EMAC_DMAINT_TBUI |EMAC_DMAINT_RI | EMAC_DMAINT_ERI)
(EMAC_DMAINT_TI | EMAC_DMAINT_TBUI | EMAC_DMAINT_RI | EMAC_DMAINT_ERI)
#define EMAC_DMAINT_ABNORMAL \
(EMAC_DMAINT_TPSI | EMAC_DMAINT_TJTI | EMAC_DMAINT_OVFI | EMAC_EMAINT_UNFI | \
@ -1574,7 +1574,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
/* Check if this is an intermediate segment in the frame */
else if (((rxdesc->rdes0 & EMAC_RDES0_LS) == 0)&&
else if (((rxdesc->rdes0 & EMAC_RDES0_LS) == 0) &&
((rxdesc->rdes0 & EMAC_RDES0_FS) == 0))
{
priv->segments++;
@ -1626,14 +1626,14 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
*/
DEBUGASSERT(dev->d_buf == NULL);
dev->d_buf = (uint8_t*)rxcurr->rdes2;
dev->d_buf = (uint8_t *)rxcurr->rdes2;
rxcurr->rdes2 = (uint32_t)buffer;
/* Return success, remebering where we should re-start scanning
* and resetting the segment scanning logic
*/
priv->rxhead = (struct emac_rxdesc_s*)rxdesc->rdes3;
priv->rxhead = (struct emac_rxdesc_s *)rxdesc->rdes3;
tiva_freesegment(priv, rxcurr, priv->segments);
nvdbg("rxhead: %p d_buf: %p d_len: %d\n",
@ -1654,7 +1654,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
/* Try the next descriptor */
rxdesc = (struct emac_rxdesc_s*)rxdesc->rdes3;
rxdesc = (struct emac_rxdesc_s *)rxdesc->rdes3;
}
/* We get here after all of the descriptors have been scanned or when rxdesc points
@ -1879,7 +1879,7 @@ static void tiva_freeframe(FAR struct tiva_ethmac_s *priv)
{
/* Yes.. Free the buffer */
tiva_freebuffer(priv, (uint8_t*)txdesc->tdes2);
tiva_freebuffer(priv, (uint8_t *)txdesc->tdes2);
}
/* In any event, make sure that TDES2 is nullified. */
@ -1912,7 +1912,7 @@ static void tiva_freeframe(FAR struct tiva_ethmac_s *priv)
/* Try the next descriptor in the TX chain */
txdesc = (struct emac_txdesc_s*)txdesc->tdes3;
txdesc = (struct emac_txdesc_s *)txdesc->tdes3;
}
/* We get here if (1) there are still frames "in-flight". Remember
@ -4207,7 +4207,7 @@ int tiva_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_PHY_IOCTL
priv->dev.d_ioctl = tiva_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void*)g_tiva_ethmac; /* Used to recover private state from dev */
priv->dev.d_private = (void *)g_tiva_ethmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */
@ -4427,7 +4427,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable)
if (enable)
{
*enable = handler ? tiva_phy_intenable : NULL;;
*enable = handler ? tiva_phy_intenable : NULL;
}
/* Return the old handler (so that it can be restored) */