sergiotarxz/nuttx
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Run files changed in last PR through tools/nxstyle, fix several coding standard violations.

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This commit is contained in:
Gregory Nutt 2019-11-21 07:50:37 -06:00
parent e1f904c943
commit 27b6132601
4 changed files with 85 additions and 78 deletions
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100
arch/arm/src/stm32f7/stm32_qspi.c
View File

@ -76,7 +76,7 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* QSPI memory synchronization */ /* QSPI memory synchronization */
#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) #define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0)
@ -211,10 +211,10 @@ struct stm32f7_qspidev_s
#endif #endif
#ifdef CONFIG_STM32F7_QSPI_REGDEBUG #ifdef CONFIG_STM32F7_QSPI_REGDEBUG
bool wrlast; /* Last was a write */ bool wrlast; /* Last was a write */
uint32_t addresslast; /* Last address */ uint32_t addresslast; /* Last address */
uint32_t valuelast; /* Last value */ uint32_t valuelast; /* Last value */
int ntimes; /* Number of times */ int ntimes; /* Number of times */
#endif #endif
}; };
@ -578,7 +578,8 @@ static void qspi_dumpgpioconfig(const char *msg)
uint32_t regval; uint32_t regval;
spiinfo("%s:\n", msg); spiinfo("%s:\n", msg);
/* port B */ /* Port B */
regval = getreg32(STM32_GPIOB_MODER); regval = getreg32(STM32_GPIOB_MODER);
spiinfo("B_MODER:%08x\n", regval); spiinfo("B_MODER:%08x\n", regval);
@ -597,7 +598,8 @@ static void qspi_dumpgpioconfig(const char *msg)
regval = getreg32(STM32_GPIOB_AFRH); regval = getreg32(STM32_GPIOB_AFRH);
spiinfo("B_AFRH:%08x\n", regval); spiinfo("B_AFRH:%08x\n", regval);
/* port D */ /* Port D */
regval = getreg32(STM32_GPIOD_MODER); regval = getreg32(STM32_GPIOD_MODER);
spiinfo("D_MODER:%08x\n", regval); spiinfo("D_MODER:%08x\n", regval);
@ -616,7 +618,8 @@ static void qspi_dumpgpioconfig(const char *msg)
regval = getreg32(STM32_GPIOD_AFRH); regval = getreg32(STM32_GPIOD_AFRH);
spiinfo("D_AFRH:%08x\n", regval); spiinfo("D_AFRH:%08x\n", regval);
/* port E */ /* Port E */
regval = getreg32(STM32_GPIOE_MODER); regval = getreg32(STM32_GPIOE_MODER);
spiinfo("E_MODER:%08x\n", regval); spiinfo("E_MODER:%08x\n", regval);
@ -1178,56 +1181,58 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
/* Is it 'Transfer Complete'? */ /* Is it 'Transfer Complete'? */
if ((status & QSPI_SR_TCF) && (cr & QSPI_CR_TCIE)) if ((status & QSPI_SR_TCF) && (cr & QSPI_CR_TCIE))
{ {
/* Acknowledge interrupt */ /* Acknowledge interrupt */
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR_OFFSET); qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR_OFFSET);
/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer
* complete Interrupts
*/
regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET);
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET);
/* Do the last bit of read if needed */ /* Do the last bit of read if needed */
if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
{ {
volatile uint32_t *datareg = volatile uint32_t *datareg =
(volatile uint32_t *)(g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); (volatile uint32_t *)(g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET);
/* Read any remaining data */ /* Read any remaining data */
while (((regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET)) & while (((regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET)) &
QSPI_SR_FLEVEL_MASK) != 0) QSPI_SR_FLEVEL_MASK) != 0)
{ {
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{ {
((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] = ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
*(volatile uint8_t *)datareg; *(volatile uint8_t *)datareg;
++g_qspi0dev.xctn->idxnow; ++g_qspi0dev.xctn->idxnow;
} }
else else
{ {
/* No room at the inn */ /* No room at the inn */
break; break;
} }
} }
} }
/* Use 'abort' to ditch any stray fifo contents and clear BUSY flag */ /* Use 'abort' to ditch any stray fifo contents and clear BUSY flag */
qspi_abort(&g_qspi0dev); qspi_abort(&g_qspi0dev);
/* Set success status */ /* Set success status */
g_qspi0dev.xctn->disposition = OK; g_qspi0dev.xctn->disposition = OK;
/* Signal complete */ /* Signal complete */
nxsem_post(&g_qspi0dev.op_sem); nxsem_post(&g_qspi0dev.op_sem);
} }
/* Is it 'Status Match'? */ /* Is it 'Status Match'? */
@ -2009,9 +2014,9 @@ static int qspi_command(struct qspi_dev_s *dev,
ret = qspi_setupxctnfromcmd(&xctn, cmdinfo); ret = qspi_setupxctnfromcmd(&xctn, cmdinfo);
if (OK != ret) if (OK != ret)
{ {
return ret; return ret;
} }
/* Prepare for transaction */ /* Prepare for transaction */
@ -2113,6 +2118,7 @@ static int qspi_command(struct qspi_dev_s *dev,
/* because command transfers are so small, we're not going to use /* because command transfers are so small, we're not going to use
* DMA for them, only interrupts or polling * DMA for them, only interrupts or polling
*/ */
#else #else
/* Polling mode */ /* Polling mode */

11
boards/arm/stm32f7/stm32f746g-disco/include/board.h
View File

@ -170,8 +170,6 @@
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
/* Configure factors for PLLI2S clock */ /* Configure factors for PLLI2S clock */
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
@ -413,12 +411,19 @@
#define BOARD_LTDC_PLLSAIR 5 #define BOARD_LTDC_PLLSAIR 5
/* Pixel Clock Polarity */ /* Pixel Clock Polarity */
#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ #define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */
/* Data Enable Polarity */ /* Data Enable Polarity */
#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ #define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */
/* Vertical Sync Polarity */ /* Vertical Sync Polarity */
#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ #define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */
/* Horicontal Sync Polarity */
/* Horizontal Sync Polarity */
#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ #define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */
/* GPIO pinset */ /* GPIO pinset */

3
boards/arm/stm32f7/stm32f746g-disco/src/stm32_bringup.c
View File

@ -95,7 +95,6 @@ int stm32_bringup(void)
"ERROR: Failed to mount the PROC filesystem: %d (%d)\n", "ERROR: Failed to mount the PROC filesystem: %d (%d)\n",
ret, errno); ret, errno);
return ret; return ret;
} }
#endif #endif
@ -142,7 +141,7 @@ int stm32_bringup(void)
#ifdef CONFIG_MTD_N25QXXX #ifdef CONFIG_MTD_N25QXXX
ret = stm32_n25qxxx_setup(); ret = stm32_n25qxxx_setup();
if (ret < 0) if (ret < 0)
{ {
syslog(LOG_ERR, "ERROR: stm32_n25qxxx_setup failed: %d\n", ret); syslog(LOG_ERR, "ERROR: stm32_n25qxxx_setup failed: %d\n", ret);
} }
#endif #endif

47
boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c
View File

@ -69,7 +69,6 @@
#include "stm32_qspi.h" #include "stm32_qspi.h"
#define HAVE_N25QXXX_NXFFS #define HAVE_N25QXXX_NXFFS
/**************************************************************************** /****************************************************************************
@ -91,46 +90,44 @@
int stm32_n25qxxx_setup(void) int stm32_n25qxxx_setup(void)
{ {
FAR struct qspi_dev_s *qspi_dev ;
FAR struct mtd_dev_s *mtd_dev;
int ret = -1;
int ret = -1; qspi_dev = stm32f7_qspi_initialize(0);
if (!qspi_dev)
FAR struct qspi_dev_s *qspi_dev = stm32f7_qspi_initialize(0);
if (!qspi_dev)
{ {
_err("ERROR: Failed to initialize W25 minor %d: %d\n", _err("ERROR: Failed to initialize W25 minor %d: %d\n",
0, ret); 0, ret);
; return -1;
return -1;
} }
FAR struct mtd_dev_s *mtd_dev = n25qxxx_initialize(qspi_dev, true); mtd_dev = n25qxxx_initialize(qspi_dev, true);
if (!mtd_dev)
if (!mtd_dev)
{ {
_err("ERROR: n25qxxx_initialize() failed!\n"); _err("ERROR: n25qxxx_initialize() failed!\n");
return -1; return -1;
} }
#ifdef HAVE_N25QXXX_NXFFS #ifdef HAVE_N25QXXX_NXFFS
/* Initialize to provide NXFFS on the N25QXXX MTD interface */ /* Initialize to provide NXFFS on the N25QXXX MTD interface */
ret = nxffs_initialize(mtd_dev); ret = nxffs_initialize(mtd_dev);
if (ret < 0) if (ret < 0)
{ {
_err("ERROR: NXFFS initialization failed: %d\n", ret); _err("ERROR: NXFFS initialization failed: %d\n", ret);
return ret; return ret;
} }
ret = mount(NULL, "/mnt/nxffs", "nxffs", 0, NULL); ret = mount(NULL, "/mnt/nxffs", "nxffs", 0, NULL);
if (ret < 0) if (ret < 0)
{ {
_err("ERROR: Failed to mount the NXFFS volume: %d\n", errno); _err("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
return ret; return ret;
} }
#endif #endif
return 0; return 0;
} }