sergiotarxz/nuttx
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Run files changed in last PR through tools/nxstyle, fix several coding standard violations.

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This commit is contained in:
Gregory Nutt 2019-11-21 07:50:37 -06:00
parent e1f904c943
commit 27b6132601
4 changed files with 85 additions and 78 deletions
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14
arch/arm/src/stm32f7/stm32_qspi.c
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@ -578,7 +578,8 @@ static void qspi_dumpgpioconfig(const char *msg)
uint32_t regval;
spiinfo("%s:\n", msg);
/* port B */
/* Port B */
regval = getreg32(STM32_GPIOB_MODER);
spiinfo("B_MODER:%08x\n", regval);
@ -597,7 +598,8 @@ static void qspi_dumpgpioconfig(const char *msg)
regval = getreg32(STM32_GPIOB_AFRH);
spiinfo("B_AFRH:%08x\n", regval);
/* port D */
/* Port D */
regval = getreg32(STM32_GPIOD_MODER);
spiinfo("D_MODER:%08x\n", regval);
@ -616,7 +618,8 @@ static void qspi_dumpgpioconfig(const char *msg)
regval = getreg32(STM32_GPIOD_AFRH);
spiinfo("D_AFRH:%08x\n", regval);
/* port E */
/* Port E */
regval = getreg32(STM32_GPIOE_MODER);
spiinfo("E_MODER:%08x\n", regval);
@ -1183,7 +1186,9 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR_OFFSET);
/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer
* complete Interrupts
*/
regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET);
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
@ -2113,6 +2118,7 @@ static int qspi_command(struct qspi_dev_s *dev,
/* because command transfers are so small, we're not going to use
* DMA for them, only interrupts or polling
*/
#else
/* Polling mode */

11
boards/arm/stm32f7/stm32f746g-disco/include/board.h
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@ -170,8 +170,6 @@
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
/* Configure factors for PLLI2S clock */
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
@ -413,12 +411,19 @@
#define BOARD_LTDC_PLLSAIR 5
/* Pixel Clock Polarity */
#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */
/* Data Enable Polarity */
#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */
/* Vertical Sync Polarity */
#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */
/* Horicontal Sync Polarity */
/* Horizontal Sync Polarity */
#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */
/* GPIO pinset */

1
boards/arm/stm32f7/stm32f746g-disco/src/stm32_bringup.c
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@ -95,7 +95,6 @@ int stm32_bringup(void)
"ERROR: Failed to mount the PROC filesystem: %d (%d)\n",
ret, errno);
return ret;
}
#endif

11
boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c
View File

@ -69,7 +69,6 @@
#include "stm32_qspi.h"
#define HAVE_N25QXXX_NXFFS
/****************************************************************************
@ -91,21 +90,19 @@
int stm32_n25qxxx_setup(void)
{
FAR struct qspi_dev_s *qspi_dev ;
FAR struct mtd_dev_s *mtd_dev;
int ret = -1;
FAR struct qspi_dev_s *qspi_dev = stm32f7_qspi_initialize(0);
qspi_dev = stm32f7_qspi_initialize(0);
if (!qspi_dev)
{
_err("ERROR: Failed to initialize W25 minor %d: %d\n",
0, ret);
;
return -1;
}
FAR struct mtd_dev_s *mtd_dev = n25qxxx_initialize(qspi_dev, true);
mtd_dev = n25qxxx_initialize(qspi_dev, true);
if (!mtd_dev)
{
_err("ERROR: n25qxxx_initialize() failed!\n");