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esp32/hardware/esp32_efuse.h: Update macros for registers.

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This commit is intended to update the EFUSE's register content and
update related configs:
 - Remove duplicated configs from `esp32_soc.h`;
 - Add missing header files from APB registers;
 - Add missing macro definitions from EFUSE;
 - Update related code to use the new macros;
This commit is contained in:
Tiago Medicci Serrano 2023-12-21 16:04:04 -03:00 committed by Xiang Xiao
parent 8752e6d863
commit 2954551ef6
9 changed files with 1771 additions and 1688 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/xtensa/src/esp32/esp32_efuse.c
View File

@ -32,6 +32,7 @@
#include "xtensa.h"
#include "esp32_efuse.h"
#include "esp32_clockconfig.h"
#include "hardware/esp32_apb_ctrl.h"
#include "hardware/esp32_efuse.h"
/****************************************************************************

2
arch/xtensa/src/esp32/esp32_efuse_table.c
View File

@ -314,7 +314,7 @@ static const efuse_desc_t SDIO_TIEH[] =
static const efuse_desc_t SDIO_FORCE[] =
{
{
144, 1 /* EFUSE_RD_SDIO_FORCE */
144, 1 /* EFUSE_RD_XPD_SDIO_FORCE */
},
};

15
arch/xtensa/src/esp32/esp32_pm.c
View File

@ -502,25 +502,22 @@ static int IRAM_ATTR esp32_get_vddsdio_config(
efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG);
if (efuse_reg & EFUSE_RD_SDIO_FORCE)
if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE)
{
/* Get configuration from EFUSE */
result->force = 0;
result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M)
>> EFUSE_RD_XPD_SDIO_REG_S;
result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M)
>> EFUSE_RD_SDIO_TIEH_S;
result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M)
>> EFUSE_RD_XPD_SDIO_TIEH_S;
if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG,
EFUSE_RD_BLK3_PART_RESERVE) == 0)
{
result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M)
>> EFUSE_RD_SDIO_DREFH_S;
result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M)
>> EFUSE_RD_SDIO_DREFM_S;
result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M)
>> EFUSE_RD_SDIO_DREFL_S;
result->drefh = (efuse_reg >> 8) & 0x3;
result->drefm = (efuse_reg >> 10) & 0x3;
result->drefl = (efuse_reg >> 12) & 0x3;
}
return OK;

21
arch/xtensa/src/esp32/esp32_psram.c
View File

@ -381,25 +381,22 @@ static int IRAM_ATTR esp32_get_vddsdio_config(
efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG);
if (efuse_reg & EFUSE_RD_SDIO_FORCE)
if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE)
{
/* Get configuration from EFUSE */
result->force = 0;
result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M)
>> EFUSE_RD_XPD_SDIO_REG_S;
result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M)
>> EFUSE_RD_SDIO_TIEH_S;
result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M)
>> EFUSE_RD_XPD_SDIO_TIEH_S;
if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG,
EFUSE_RD_BLK3_PART_RESERVE) == 0)
{
result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M)
>> EFUSE_RD_SDIO_DREFH_S;
result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M)
>> EFUSE_RD_SDIO_DREFM_S;
result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M)
>> EFUSE_RD_SDIO_DREFL_S;
result->drefh = (efuse_reg >> 8) & 0x3;
result->drefm = (efuse_reg >> 10) & 0x3;
result->drefl = (efuse_reg >> 12) & 0x3;
}
return OK;
@ -1514,8 +1511,10 @@ psram_enable(int mode, int vaddrmode) /* psram init */
0
};
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG,
EFUSE_RD_CHIP_VER_PKG);
uint32_t chip_ver = (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG,
EFUSE_RD_CHIP_PACKAGE_4BIT) << 3) |
REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG,
EFUSE_RD_CHIP_PACKAGE);
uint32_t pkg_ver = chip_ver & 0x7;
uint32_t spiconfig;

1
arch/xtensa/src/esp32/esp32_rtc.c
View File

@ -34,6 +34,7 @@
#include "esp32_clockconfig.h"
#include "esp32_rt_timer.h"
#include "hardware/esp32_apb_ctrl.h"
#include "hardware/esp32_rtccntl.h"
#include "hardware/esp32_rtc_io.h"
#include "hardware/esp32_dport.h"

422
arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h Normal file
View File

@ -0,0 +1,422 @@
/****************************************************************************
* arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H
#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* APB_CTRL_SYSCLK_CONF_REG register */
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
/* APB_CTRL_QUICK_CLK_CHNG : RW; bitpos: [13]; default: 1; */
#define APB_CTRL_QUICK_CLK_CHNG (BIT(13))
#define APB_CTRL_QUICK_CLK_CHNG_M (APB_CTRL_QUICK_CLK_CHNG_V << APB_CTRL_QUICK_CLK_CHNG_S)
#define APB_CTRL_QUICK_CLK_CHNG_V 0x00000001
#define APB_CTRL_QUICK_CLK_CHNG_S 13
/* APB_CTRL_RST_TICK_CNT : RW; bitpos: [12]; default: 0; */
#define APB_CTRL_RST_TICK_CNT (BIT(12))
#define APB_CTRL_RST_TICK_CNT_M (APB_CTRL_RST_TICK_CNT_V << APB_CTRL_RST_TICK_CNT_S)
#define APB_CTRL_RST_TICK_CNT_V 0x00000001
#define APB_CTRL_RST_TICK_CNT_S 12
/* APB_CTRL_CLK_EN : RW; bitpos: [11]; default: 0; */
#define APB_CTRL_CLK_EN (BIT(11))
#define APB_CTRL_CLK_EN_M (APB_CTRL_CLK_EN_V << APB_CTRL_CLK_EN_S)
#define APB_CTRL_CLK_EN_V 0x00000001
#define APB_CTRL_CLK_EN_S 11
/* APB_CTRL_CLK_320M_EN : RW; bitpos: [10]; default: 0; */
#define APB_CTRL_CLK_320M_EN (BIT(10))
#define APB_CTRL_CLK_320M_EN_M (APB_CTRL_CLK_320M_EN_V << APB_CTRL_CLK_320M_EN_S)
#define APB_CTRL_CLK_320M_EN_V 0x00000001
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : RW; bitpos: [9:0]; default: 0; */
#define APB_CTRL_PRE_DIV_CNT 0x000003ff
#define APB_CTRL_PRE_DIV_CNT_M (APB_CTRL_PRE_DIV_CNT_V << APB_CTRL_PRE_DIV_CNT_S)
#define APB_CTRL_PRE_DIV_CNT_V 0x000003ff
#define APB_CTRL_PRE_DIV_CNT_S 0
/* APB_CTRL_XTAL_TICK_CONF_REG register */
#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
/* APB_CTRL_XTAL_TICK_NUM : RW; bitpos: [7:0]; default: 39; */
#define APB_CTRL_XTAL_TICK_NUM 0x000000ff
#define APB_CTRL_XTAL_TICK_NUM_M (APB_CTRL_XTAL_TICK_NUM_V << APB_CTRL_XTAL_TICK_NUM_S)
#define APB_CTRL_XTAL_TICK_NUM_V 0x000000ff
#define APB_CTRL_XTAL_TICK_NUM_S 0
/* APB_CTRL_PLL_TICK_CONF_REG register */
#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8)
/* APB_CTRL_PLL_TICK_NUM : RW; bitpos: [7:0]; default: 79; */
#define APB_CTRL_PLL_TICK_NUM 0x000000ff
#define APB_CTRL_PLL_TICK_NUM_M (APB_CTRL_PLL_TICK_NUM_V << APB_CTRL_PLL_TICK_NUM_S)
#define APB_CTRL_PLL_TICK_NUM_V 0x000000ff
#define APB_CTRL_PLL_TICK_NUM_S 0
/* APB_CTRL_CK8M_TICK_CONF_REG register */
#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xc)
/* APB_CTRL_CK8M_TICK_NUM : RW; bitpos: [7:0]; default: 11; */
#define APB_CTRL_CK8M_TICK_NUM 0x000000ff
#define APB_CTRL_CK8M_TICK_NUM_M (APB_CTRL_CK8M_TICK_NUM_V << APB_CTRL_CK8M_TICK_NUM_S)
#define APB_CTRL_CK8M_TICK_NUM_V 0x000000ff
#define APB_CTRL_CK8M_TICK_NUM_S 0
/* APB_CTRL_APB_SARADC_CTRL_REG register */
#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10)
/* APB_CTRL_SARADC_DATA_TO_I2S : RW; bitpos: [26]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from
* GPIO matrix
*/
#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26))
#define APB_CTRL_SARADC_DATA_TO_I2S_M (APB_CTRL_SARADC_DATA_TO_I2S_V << APB_CTRL_SARADC_DATA_TO_I2S_S)
#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x00000001
#define APB_CTRL_SARADC_DATA_TO_I2S_S 26
/* APB_CTRL_SARADC_DATA_SAR_SEL : RW; bitpos: [25]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data in this
* case the resolution should not be larger than 11 bits.
*/
#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25))
#define APB_CTRL_SARADC_DATA_SAR_SEL_M (APB_CTRL_SARADC_DATA_SAR_SEL_V << APB_CTRL_SARADC_DATA_SAR_SEL_S)
#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x00000001
#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25
/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : RW; bitpos: [24]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V << APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S)
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x00000001
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : RW; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V << APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S)
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x00000001
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23
/* APB_CTRL_SARADC_SAR2_PATT_LEN : RW; bitpos: [22:19]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000f
#define APB_CTRL_SARADC_SAR2_PATT_LEN_M (APB_CTRL_SARADC_SAR2_PATT_LEN_V << APB_CTRL_SARADC_SAR2_PATT_LEN_S)
#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0x0000000f
#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19
/* APB_CTRL_SARADC_SAR1_PATT_LEN : RW; bitpos: [18:15]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000f
#define APB_CTRL_SARADC_SAR1_PATT_LEN_M (APB_CTRL_SARADC_SAR1_PATT_LEN_V << APB_CTRL_SARADC_SAR1_PATT_LEN_S)
#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0x0000000f
#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15
/* APB_CTRL_SARADC_SAR_CLK_DIV : RW; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000ff
#define APB_CTRL_SARADC_SAR_CLK_DIV_M (APB_CTRL_SARADC_SAR_CLK_DIV_V << APB_CTRL_SARADC_SAR_CLK_DIV_S)
#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0x000000ff
#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7
/* APB_CTRL_SARADC_SAR_CLK_GATED : RW; bitpos: [6]; default: 1; */
#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_CTRL_SARADC_SAR_CLK_GATED_M (APB_CTRL_SARADC_SAR_CLK_GATED_V << APB_CTRL_SARADC_SAR_CLK_GATED_S)
#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x00000001
#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6
/* APB_CTRL_SARADC_SAR_SEL : RW; bitpos: [5]; default: 0;
* 0: SAR1 1: SAR2 only work for single SAR mode
*/
#define APB_CTRL_SARADC_SAR_SEL (BIT(5))
#define APB_CTRL_SARADC_SAR_SEL_M (APB_CTRL_SARADC_SAR_SEL_V << APB_CTRL_SARADC_SAR_SEL_S)
#define APB_CTRL_SARADC_SAR_SEL_V 0x00000001
#define APB_CTRL_SARADC_SAR_SEL_S 5
/* APB_CTRL_SARADC_WORK_MODE : RW; bitpos: [4:3]; default: 0;
* 0: single mode 1: double mode 2: alternate mode
*/
#define APB_CTRL_SARADC_WORK_MODE 0x00000003
#define APB_CTRL_SARADC_WORK_MODE_M (APB_CTRL_SARADC_WORK_MODE_V << APB_CTRL_SARADC_WORK_MODE_S)
#define APB_CTRL_SARADC_WORK_MODE_V 0x00000003
#define APB_CTRL_SARADC_WORK_MODE_S 3
/* APB_CTRL_SARADC_SAR2_MUX : RW; bitpos: [2]; default: 0;
* 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by
* PWDET CTRL
*/
#define APB_CTRL_SARADC_SAR2_MUX (BIT(2))
#define APB_CTRL_SARADC_SAR2_MUX_M (APB_CTRL_SARADC_SAR2_MUX_V << APB_CTRL_SARADC_SAR2_MUX_S)
#define APB_CTRL_SARADC_SAR2_MUX_V 0x00000001
#define APB_CTRL_SARADC_SAR2_MUX_S 2
/* APB_CTRL_SARADC_START : RW; bitpos: [1]; default: 0; */
#define APB_CTRL_SARADC_START (BIT(1))
#define APB_CTRL_SARADC_START_M (APB_CTRL_SARADC_START_V << APB_CTRL_SARADC_START_S)
#define APB_CTRL_SARADC_START_V 0x00000001
#define APB_CTRL_SARADC_START_S 1
/* APB_CTRL_SARADC_START_FORCE : RW; bitpos: [0]; default: 0; */
#define APB_CTRL_SARADC_START_FORCE (BIT(0))
#define APB_CTRL_SARADC_START_FORCE_M (APB_CTRL_SARADC_START_FORCE_V << APB_CTRL_SARADC_START_FORCE_S)
#define APB_CTRL_SARADC_START_FORCE_V 0x00000001
#define APB_CTRL_SARADC_START_FORCE_S 0
/* APB_CTRL_APB_SARADC_CTRL2_REG register */
#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14)
/* APB_CTRL_SARADC_SAR2_INV : RW; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted otherwise not
*/
#define APB_CTRL_SARADC_SAR2_INV (BIT(10))
#define APB_CTRL_SARADC_SAR2_INV_M (APB_CTRL_SARADC_SAR2_INV_V << APB_CTRL_SARADC_SAR2_INV_S)
#define APB_CTRL_SARADC_SAR2_INV_V 0x00000001
#define APB_CTRL_SARADC_SAR2_INV_S 10
/* APB_CTRL_SARADC_SAR1_INV : RW; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted otherwise not
*/
#define APB_CTRL_SARADC_SAR1_INV (BIT(9))
#define APB_CTRL_SARADC_SAR1_INV_M (APB_CTRL_SARADC_SAR1_INV_V << APB_CTRL_SARADC_SAR1_INV_S)
#define APB_CTRL_SARADC_SAR1_INV_V 0x00000001
#define APB_CTRL_SARADC_SAR1_INV_S 9
/* APB_CTRL_SARADC_MAX_MEAS_NUM : RW; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000ff
#define APB_CTRL_SARADC_MAX_MEAS_NUM_M (APB_CTRL_SARADC_MAX_MEAS_NUM_V << APB_CTRL_SARADC_MAX_MEAS_NUM_S)
#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0x000000ff
#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1
/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : RW; bitpos: [0]; default: 0; */
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (APB_CTRL_SARADC_MEAS_NUM_LIMIT_V << APB_CTRL_SARADC_MEAS_NUM_LIMIT_S)
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x00000001
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0
/* APB_CTRL_APB_SARADC_FSM_REG register */
#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18)
/* APB_CTRL_SARADC_SAMPLE_CYCLE : RW; bitpos: [31:24]; default: 2;
* sample cycles
*/
#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000ff
#define APB_CTRL_SARADC_SAMPLE_CYCLE_M (APB_CTRL_SARADC_SAMPLE_CYCLE_V << APB_CTRL_SARADC_SAMPLE_CYCLE_S)
#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0x000000ff
#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24
/* APB_CTRL_SARADC_START_WAIT : RW; bitpos: [23:16]; default: 8; */
#define APB_CTRL_SARADC_START_WAIT 0x000000ff
#define APB_CTRL_SARADC_START_WAIT_M (APB_CTRL_SARADC_START_WAIT_V << APB_CTRL_SARADC_START_WAIT_S)
#define APB_CTRL_SARADC_START_WAIT_V 0x000000ff
#define APB_CTRL_SARADC_START_WAIT_S 16
/* APB_CTRL_SARADC_STANDBY_WAIT : RW; bitpos: [15:8]; default: 255; */
#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000ff
#define APB_CTRL_SARADC_STANDBY_WAIT_M (APB_CTRL_SARADC_STANDBY_WAIT_V << APB_CTRL_SARADC_STANDBY_WAIT_S)
#define APB_CTRL_SARADC_STANDBY_WAIT_V 0x000000ff
#define APB_CTRL_SARADC_STANDBY_WAIT_S 8
/* APB_CTRL_SARADC_RSTB_WAIT : RW; bitpos: [7:0]; default: 8; */
#define APB_CTRL_SARADC_RSTB_WAIT 0x000000ff
#define APB_CTRL_SARADC_RSTB_WAIT_M (APB_CTRL_SARADC_RSTB_WAIT_V << APB_CTRL_SARADC_RSTB_WAIT_S)
#define APB_CTRL_SARADC_RSTB_WAIT_V 0x000000ff
#define APB_CTRL_SARADC_RSTB_WAIT_S 0
/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG register */
#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1c)
/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : RW; bitpos: [31:0]; default: 252645135;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M (APB_CTRL_SARADC_SAR1_PATT_TAB1_V << APB_CTRL_SARADC_SAR1_PATT_TAB1_S)
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0
/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG register */
#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20)
/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : RW; bitpos: [31:0]; default: 252645135;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M (APB_CTRL_SARADC_SAR1_PATT_TAB2_V << APB_CTRL_SARADC_SAR1_PATT_TAB2_S)
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0
/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG register */
#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24)
/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : RW; bitpos: [31:0]; default: 252645135;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M (APB_CTRL_SARADC_SAR1_PATT_TAB3_V << APB_CTRL_SARADC_SAR1_PATT_TAB3_S)
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0
/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG register */
#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28)
/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : RW; bitpos: [31:0]; default: 252645135;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M (APB_CTRL_SARADC_SAR1_PATT_TAB4_V << APB_CTRL_SARADC_SAR1_PATT_TAB4_S)
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xffffffff
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0
/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG register */
#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2c)
/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : RW; bitpos: [31:0]; default: 252645135;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M (APB_CTRL_SARADC_SAR2_PATT_TAB1_V << APB_CTRL_SARADC_SAR2_PATT_TAB1_S)
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0
/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG register */
#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30)
/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : RW; bitpos: [31:0]; default: 252645135;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M (APB_CTRL_SARADC_SAR2_PATT_TAB2_V << APB_CTRL_SARADC_SAR2_PATT_TAB2_S)
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0
/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG register */
#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34)
/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : RW; bitpos: [31:0]; default: 252645135;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M (APB_CTRL_SARADC_SAR2_PATT_TAB3_V << APB_CTRL_SARADC_SAR2_PATT_TAB3_S)
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0
/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG register */
#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38)
/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : RW; bitpos: [31:0]; default: 252645135;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M (APB_CTRL_SARADC_SAR2_PATT_TAB4_V << APB_CTRL_SARADC_SAR2_PATT_TAB4_S)
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xffffffff
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0
/* APB_CTRL_APLL_TICK_CONF_REG register */
#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3c)
/* APB_CTRL_APLL_TICK_NUM : RW; bitpos: [7:0]; default: 99; */
#define APB_CTRL_APLL_TICK_NUM 0x000000ff
#define APB_CTRL_APLL_TICK_NUM_M (APB_CTRL_APLL_TICK_NUM_V << APB_CTRL_APLL_TICK_NUM_S)
#define APB_CTRL_APLL_TICK_NUM_V 0x000000ff
#define APB_CTRL_APLL_TICK_NUM_S 0
/* APB_CTRL_DATE_REG register */
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7c)
/* APB_CTRL_DATE : RW; bitpos: [31:0]; default: 369369088; */
#define APB_CTRL_DATE 0xffffffff
#define APB_CTRL_DATE_M (APB_CTRL_DATE_V << APB_CTRL_DATE_S)
#define APB_CTRL_DATE_V 0xffffffff
#define APB_CTRL_DATE_S 0
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H */

2834
arch/xtensa/src/esp32/hardware/esp32_efuse.h
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File diff suppressed because it is too large Load Diff

73
arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h Normal file
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@ -0,0 +1,73 @@
/****************************************************************************
* arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H
#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
/* Write disable bits */
#define EFUSE_WR_DIS_RD_DIS (1 << 0) /* disable writing read disable reg */
#define EFUSE_WR_DIS_WR_DIS (1 << 1) /* disable writing write disable reg */
#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1 << 2)
#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1 << 3) /* disable writing MAC & SPI config hd efuses */
#define EFUSE_WR_DIS_XPD_SDIO (1 << 5) /* disable writing SDIO config efuses */
#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1 << 6) /* disable writing SPI_PAD_CONFIG efuses */
#define EFUSE_WR_DIS_BLK1 (1 << 7) /* disable writing BLK1 efuses */
#define EFUSE_WR_DIS_BLK2 (1 << 8) /* disable writing BLK2 efuses */
#define EFUSE_WR_DIS_BLK3 (1 << 9) /* disable writing BLK3 efuses */
#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1 << 10) /* disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */
#define EFUSE_WR_DIS_ABS_DONE_0 (1 << 12) /* disable writing ABS_DONE_0 efuse */
#define EFUSE_WR_DIS_ABS_DONE_1 (1 << 13) /* disable writing ABS_DONE_1 efuse */
#define EFUSE_WR_DIS_JTAG_DISABLE (1 << 14) /* disable writing JTAG_DISABLE efuse */
#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1 << 15) /* disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */
/* Read disable bits for efuse blocks 1-3 */
#define EFUSE_RD_DIS_BLK1 (1 << 16)
#define EFUSE_RD_DIS_BLK2 (1 << 17)
#define EFUSE_RD_DIS_BLK3 (1 << 18)
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1
#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */
#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7
#define EFUSE_CODING_SCHEME_VAL_NONE 0x0
#define EFUSE_CODING_SCHEME_VAL_34 0x1
#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H */

90
arch/xtensa/src/esp32/hardware/esp32_soc.h
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@ -29,6 +29,8 @@
#include <stdbool.h>
#include "xtensa_attr.h"
#include "hardware/esp32_efuse.h"
#include <nuttx/bits.h>
/****************************************************************************
@ -366,8 +368,6 @@
#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */
#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */
#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010)
#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
/* Interrupt cpu using table */
@ -430,14 +430,6 @@
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
#define APB_CTRL_PRE_DIV_CNT 0x000003ff
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << \
(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3ff
#define APB_CTRL_PRE_DIV_CNT_S 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_OC_ENB_FCAL 4
@ -487,84 +479,6 @@ extern int rom_i2c_writereg(int block, int block_id, int reg_add,
#define BBPLL_OC_ENB_VCON_VAL 0x00
#define BBPLL_BBADC_CAL_7_0_VAL 0x00
#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
/* description: This field stores the voltage level for
* CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
* 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
*/
#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S))
#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */
/* description: read for sdio_force */
#define EFUSE_RD_SDIO_FORCE (BIT(16))
#define EFUSE_RD_SDIO_FORCE_M (BIT(16))
#define EFUSE_RD_SDIO_FORCE_V 0x1
#define EFUSE_RD_SDIO_FORCE_S 16
/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */
/* description: read for XPD_SDIO_REG */
#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_V 0x1
#define EFUSE_RD_XPD_SDIO_REG_S 14
/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */
/* description: read for SDIO_TIEH */
#define EFUSE_RD_SDIO_TIEH (BIT(15))
#define EFUSE_RD_SDIO_TIEH_M (BIT(15))
#define EFUSE_RD_SDIO_TIEH_V 0x1
#define EFUSE_RD_SDIO_TIEH_S 15
/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
/* description: If set, this bit indicates that
* BLOCK3[143:96] is reserved for internal use
*/
#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14))
#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S))
#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1
#define EFUSE_RD_BLK3_PART_RESERVE_S 14
/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFH 0x00000003
#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S))
#define EFUSE_RD_SDIO_DREFH_V 0x3
#define EFUSE_RD_SDIO_DREFH_S 8
/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFM 0x00000003
#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S))
#define EFUSE_RD_SDIO_DREFM_V 0x3
#define EFUSE_RD_SDIO_DREFM_S 10
/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space.
* Newer versions of ESP32 come with EFUSE_ADC_VREF already burned,
* therefore SDIO_DREFH/M/L is only available in older versions of ESP32
*/
/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFL 0x00000003
#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S))
#define EFUSE_RD_SDIO_DREFL_V 0x3
#define EFUSE_RD_SDIO_DREFL_S 12
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)