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* kinetis:PIT add Liftime and Chaining

    * kinetis:flexcan fix dup line and ordering

    * kinetis:kinetis_lowput.c LPUART data format with parity fix

          The 9-bit data mode is typically used with parity to allow
          eight bits of data plus the parity

    * kinetis:pindma fix warning

    * kinetis:lowputc  LPUART_BAUD_INIT has to be defined

           build fails with test case enable LPUART0 and make
           UART1 console

           if HAVE_LPUART_DEVICE is defined then LPUART_BAUD_INIT
           has to be defined even if the lpuart is not the console

    * kinetis:lpserial fix warning
This commit is contained in:
David Sidrane 2018-08-09 09:08:39 -06:00 committed by Gregory Nutt
parent 48a030f7f0
commit 2e23ffe9d2
5 changed files with 63 additions and 42 deletions
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10
arch/arm/src/kinetis/chip/kinetis_flexcan.h
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@ -280,17 +280,17 @@
#define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */ #define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */
#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */ #define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */
/* Bit 15: Reserved */ /* Bit 15: Reserved */
#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */
#define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-22: Lowest Priority Tx Mailbox */ #define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-22: Lowest Priority Tx Mailbox */
#define CAN_ESR2_LPTM_MASK (0x7f << CAN_ESR2_LPTM_SHIFT) #define CAN_ESR2_LPTM_MASK (0x7f << CAN_ESR2_LPTM_SHIFT)
/* Bits 23-31: Reserved */ /* Bits 23-31: Reserved */
/* CRC Register */ /* CRC Register */
/* Bits 23-31: Reserved */
#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */
#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT)
/* Bit 15: Reserved */
#define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-14: CRC Transmitted */ #define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-14: CRC Transmitted */
#define CAN_CRCR_TXCRC_MASK (0x7fff << CAN_CRCR_TXCRC_SHIFT) #define CAN_CRCR_TXCRC_MASK (0x7fff << CAN_CRCR_TXCRC_SHIFT)
/* Bit 15: Reserved */
#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */
#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT)
/* Bits 23-31: Reserved */
/* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */ /* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */

85
arch/arm/src/kinetis/chip/kinetis_pit.h
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@ -48,45 +48,58 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
#if defined(KINETIS_K66)
# define KINETIS_PIT_HAS_CHAIN
# define KINETIS_PIT_HAS_LIFETIME
#endif
/* Register Offsets *****************************************************************/ /* Register Offsets *****************************************************************/
#define KINETIS_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */ #define KINETIS_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */
#define KINETIS_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */ #if defined(KINETIS_PIT_HAS_LIFETIME)
#define KINETIS_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */ # define KINETIS_PIT_LTMR64H_OFFSET 0x00e0 /* PIT Upper Lifetime Timer Register */
#define KINETIS_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */ # define KINETIS_PIT_LTMR64L_OFFSET 0x00e4 /* PIT Lower Lifetime Timer Register */
#define KINETIS_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */ #endif
#define KINETIS_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */ #define KINETIS_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */
#define KINETIS_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */ #define KINETIS_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */
#define KINETIS_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */ #define KINETIS_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */
#define KINETIS_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */ #define KINETIS_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */
#define KINETIS_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */ #define KINETIS_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */
#define KINETIS_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */ #define KINETIS_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */
#define KINETIS_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */ #define KINETIS_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */
#define KINETIS_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */ #define KINETIS_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */
#define KINETIS_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */ #define KINETIS_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */
#define KINETIS_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */ #define KINETIS_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */
#define KINETIS_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */ #define KINETIS_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */
#define KINETIS_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */ #define KINETIS_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */
#define KINETIS_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */
#define KINETIS_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */
#define KINETIS_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */
#define KINETIS_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */
/* Register Addresses ***************************************************************/ /* Register Addresses ***************************************************************/
#define KINETIS_PIT_MCR (KINETIS_PIT_BASE+KINETIS_PIT_MCR_OFFSET) #define KINETIS_PIT_MCR (KINETIS_PIT_BASE+KINETIS_PIT_MCR_OFFSET)
#define KINETIS_PIT_LDVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL0_OFFSET) #if defined(KINETIS_PIT_HAS_LIFETIME)
#define KINETIS_PIT_CVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL0_OFFSET) # define KINETIS_PIT_LTMR64H (KINETIS_PIT_BASE+KINETIS_PIT_LTMR64H_OFFSET)
#define KINETIS_PIT_TCTRL0 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL0_OFFSET) # define KINETIS_PIT_LTMR64L (KINETIS_PIT_BASE+KINETIS_PIT_LTMR64L_OFFSET)
#define KINETIS_PIT_TFLG0 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG0_OFFSET) #endif
#define KINETIS_PIT_LDVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL1_OFFSET) #define KINETIS_PIT_LDVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL0_OFFSET)
#define KINETIS_PIT_CVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL1_OFFSET) #define KINETIS_PIT_CVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL0_OFFSET)
#define KINETIS_PIT_TCTRL1 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL1_OFFSET) #define KINETIS_PIT_TCTRL0 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL0_OFFSET)
#define KINETIS_PIT_TFLG1 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG1_OFFSET) #define KINETIS_PIT_TFLG0 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG0_OFFSET)
#define KINETIS_PIT_LDVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL2_OFFSET) #define KINETIS_PIT_LDVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL1_OFFSET)
#define KINETIS_PIT_CVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL2_OFFSET) #define KINETIS_PIT_CVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL1_OFFSET)
#define KINETIS_PIT_TCTRL2 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL2_OFFSET) #define KINETIS_PIT_TCTRL1 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL1_OFFSET)
#define KINETIS_PIT_TFLG2 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG2_OFFSET) #define KINETIS_PIT_TFLG1 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG1_OFFSET)
#define KINETIS_PIT_LDVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL3_OFFSET) #define KINETIS_PIT_LDVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL2_OFFSET)
#define KINETIS_PIT_CVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL3_OFFSET) #define KINETIS_PIT_CVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL2_OFFSET)
#define KINETIS_PIT_TCTRL3 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL3_OFFSET) #define KINETIS_PIT_TCTRL2 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL2_OFFSET)
#define KINETIS_PIT_TFLG3 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG3_OFFSET) #define KINETIS_PIT_TFLG2 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG2_OFFSET)
#define KINETIS_PIT_LDVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL3_OFFSET)
#define KINETIS_PIT_CVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL3_OFFSET)
#define KINETIS_PIT_TCTRL3 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL3_OFFSET)
#define KINETIS_PIT_TFLG3 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG3_OFFSET)
/* Register Bit Definitions *********************************************************/ /* Register Bit Definitions *********************************************************/
@ -104,6 +117,10 @@
#define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable Bit */ #define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable Bit */
#define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable Bit */ #define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable Bit */
/* Bits 2-31: Reserved */ /* Bits 2-31: Reserved */
#if defined(KINETIS_PIT_HAS_CHAIN)
#define PIT_TCTRL_CHN (1 << 2) /* Bit 2: Chain Mode */
/* Bits 3-31: Reserved */
#endif
/* Timer Flag Register */ /* Timer Flag Register */
#define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */ #define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */

4
arch/arm/src/kinetis/kinetis_lowputc.c
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@ -245,6 +245,8 @@
# if ((CONSOLE_FREQ / (CONSOLE_BAUD * 32)) > (LPUART_BAUD_SBR_MASK >> LPUART_BAUD_SBR_SHIFT)) # if ((CONSOLE_FREQ / (CONSOLE_BAUD * 32)) > (LPUART_BAUD_SBR_MASK >> LPUART_BAUD_SBR_SHIFT))
# error "LPUART Console: Baud rate not obtainable with this input clock!" # error "LPUART Console: Baud rate not obtainable with this input clock!"
# endif # endif
#endif
#ifdef HAVE_LPUART_DEVICE
# define LPUART_BAUD_INIT (LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS | \ # define LPUART_BAUD_INIT (LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS | \
LPUART_BAUD_RXEDGIE | LPUART_BAUD_LBKDIE | \ LPUART_BAUD_RXEDGIE | LPUART_BAUD_LBKDIE | \
LPUART_BAUD_RESYNCDIS |LPUART_BAUD_BOTHEDGE | \ LPUART_BAUD_RESYNCDIS |LPUART_BAUD_BOTHEDGE | \
@ -933,7 +935,7 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
/* Check for 9-bit operation */ /* Check for 9-bit operation */
if (nbits == 9) if (nbits == 9 || (nbits == 8 && parity != 0))
{ {
regval |= LPUART_CTRL_M; regval |= LPUART_CTRL_M;
} }

2
arch/arm/src/kinetis/kinetis_lpserial.c
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@ -570,6 +570,7 @@ static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie)
* Name: kinetis_disableuartint * Name: kinetis_disableuartint
****************************************************************************/ ****************************************************************************/
#if defined(HAVE_LPUART_PUTC) && defined(HAVE_LPUART_CONSOLE)
static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie) static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie)
{ {
irqstate_t flags; irqstate_t flags;
@ -583,6 +584,7 @@ static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie)
kinetis_restoreuartint(priv, 0); kinetis_restoreuartint(priv, 0);
leave_critical_section(flags); leave_critical_section(flags);
} }
#endif
/**************************************************************************** /****************************************************************************
* Name: kinetis_setup * Name: kinetis_setup

4
arch/arm/src/kinetis/kinetis_pindma.c
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@ -47,14 +47,14 @@
#include <arch/board/board.h> #include <arch/board/board.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/arch.h>
#include "up_arch.h"
#include "up_internal.h" #include "up_internal.h"
#include "kinetis_config.h" #include "kinetis_config.h"
#include "chip.h" #include "chip.h"
#include "kinetis.h" #include "kinetis.h"
#ifdef CONFIG_KINETIS_DMA #ifdef CONFIG_KINETIS_DMA
/**************************************************************************** /****************************************************************************