configs/nucleo-144: Test F7 SPI
This commit is contained in:
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ccfcb12ef7
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@ -21,6 +21,7 @@ Contents
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- U[S]ARTs and Serial Consoles
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- U[S]ARTs and Serial Consoles
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- SPI
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- SPI
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- SDIO - MMC
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- SDIO - MMC
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- SPI Test
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- Configurations
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- Configurations
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f7xx-nsh
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f7xx-nsh
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f7xx-evalos
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f7xx-evalos
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@ -437,6 +438,40 @@ SDIO
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DAT2 PC10 CN11-1
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DAT2 PC10 CN11-1
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CD PC11 CN11-2
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CD PC11 CN11-2
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SPI Test
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========
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The builtin SPI test facility can be enabled with the following settings:
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+CONFIG_STM32F7_SPI=y
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+CONFIG_STM32F7_SPI1=y
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+CONFIG_STM32F7_SPI2=y
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+CONFIG_STM32F7_SPI3=y
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+# CONFIG_STM32F7_SPI_INTERRUPTS is not set
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+# CONFIG_STM32F7_SPI_DMA is not set
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# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
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+CONFIG_NUCLEO_SPI_TEST=y
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+CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World"
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+CONFIG_NUCLEO_SPI1_TEST=y
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+CONFIG_NUCLEO_SPI1_TEST_FREQ=1000000
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+CONFIG_NUCLEO_SPI1_TEST_BITS=8
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+CONFIG_NUCLEO_SPI1_TEST_MODE3=y
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+CONFIG_NUCLEO_SPI2_TEST=y
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+CONFIG_NUCLEO_SPI2_TEST_FREQ=12000000
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+CONFIG_NUCLEO_SPI2_TEST_BITS=8
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+CONFIG_NUCLEO_SPI2_TEST_MODE3=y
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+CONFIG_NUCLEO_SPI3_TEST=y
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+CONFIG_NUCLEO_SPI3_TEST_FREQ=40000000
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+CONFIG_NUCLEO_SPI3_TEST_BITS=8
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+CONFIG_NUCLEO_SPI3_TEST_MODE3=y
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+CONFIG_LIB_BOARDCTL=y
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+CONFIG_NSH_ARCHINIT=y
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Configurations
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Configurations
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==============
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==============
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@ -296,6 +296,7 @@
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/* USART3:
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/* USART3:
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* Use USART3 and the USB virtual COM port
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* Use USART3 and the USB virtual COM port
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*/
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*/
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#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
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#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
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# define GPIO_USART3_RX GPIO_USART3_RX_3
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# define GPIO_USART3_RX GPIO_USART3_RX_3
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# define GPIO_USART3_TX GPIO_USART3_TX_3
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# define GPIO_USART3_TX GPIO_USART3_TX_3
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@ -307,9 +308,36 @@
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* with the serial interface with the adaptor's RX on pin CN11 pin 64 and
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* with the serial interface with the adaptor's RX on pin CN11 pin 64 and
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* TX on pin CN11 pin 61
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* TX on pin CN11 pin 61
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*
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*
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* USART8: has noit remap
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* USART8: has no remap
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*/
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*/
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/* SPI
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*
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*
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* PA6 MISO CN12-13
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* PA7 MOSI CN12-15
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* PA5 SCK CN12-11
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*
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* PB14 MISO CN12-28
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* PB15 MOSI CN12-26
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* PB10 SCK CN12-25
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*
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* PB4 MISO CN12-27
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* PB5 MOSI CN12-29
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* PB3 SCK CN12-31
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
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/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
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/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
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*
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*
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@ -102,11 +102,11 @@
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GPIO_OUTPUT_SET)
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GPIO_OUTPUT_SET)
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#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
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#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
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#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13)
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#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
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#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13)
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#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
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#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
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#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
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#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
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#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
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#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
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#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
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#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
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#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
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#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
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#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
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#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
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#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
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@ -164,7 +164,7 @@ void stm32_spidev_initialize(void);
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*
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*
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************************************************************************************/
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************************************************************************************/
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#if defined(NUCLEO_SPI_TEST)
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#if defined(CONFIG_NUCLEO_SPI_TEST)
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int stm32_spidev_bus_test(void);
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int stm32_spidev_bus_test(void);
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#endif
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#endif
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@ -111,10 +111,10 @@ int board_app_initialize(uintptr_t arg)
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#if defined(CONFIG_NUCLEO_SPI_TEST)
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#if defined(CONFIG_NUCLEO_SPI_TEST)
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/* Create SPI interfaces */
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/* Create SPI interfaces */
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ret = stm32_spidev_bus_init();
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ret = stm32_spidev_bus_test();
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if (ret != OK)
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if (ret != OK)
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{
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{
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ferr("ERROR: Failed to initialize SPI interfaces: %d\n", ret);
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syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", ret);
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return ret;
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return ret;
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}
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}
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#endif
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#endif
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@ -70,7 +70,7 @@ void stm32_boardinitialize(void)
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board_autoled_initialize();
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board_autoled_initialize();
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#endif
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#endif
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#if defined(CONFIG__SPI)
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#if defined(CONFIG_SPI)
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/* Configure SPI chip selects */
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/* Configure SPI chip selects */
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stm32_spidev_initialize();
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stm32_spidev_initialize();
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@ -228,7 +228,7 @@ void weak_function stm32_spidev_initialize(void)
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void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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{
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[i], !selected);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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}
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}
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uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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@ -241,7 +241,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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{
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[i], !selected);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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}
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}
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uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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@ -254,7 +254,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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{
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[i], !selected);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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}
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}
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uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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@ -271,7 +271,7 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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{
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[i], !selected);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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}
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}
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uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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@ -288,7 +288,7 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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{
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[i], !selected);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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}
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}
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uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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@ -304,7 +304,7 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
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{
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{
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[i], !selected);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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}
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}
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uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
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@ -382,11 +382,11 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
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#endif /* CONFIG_SPI_CMDDATA */
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#endif /* CONFIG_SPI_CMDDATA */
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#if defined(CONFIG_NUCLEO_SPI_TEST)
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#if defined(CONFIG_NUCLEO_SPI_TEST)
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int stm32_spidev_bus_init(void)
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int stm32_spidev_bus_test(void)
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{
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{
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/* Configure and test SPI-*/
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/* Configure and test SPI-*/
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uint8_t *tx = CONFIG_NUCLEO_SPI_TEST_MESSAGE;
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uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE;
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#if defined(CONFIG_NUCLEO_SPI1_TEST)
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#if defined(CONFIG_NUCLEO_SPI1_TEST)
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spi1 = stm32_spibus_initialize(1);
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spi1 = stm32_spibus_initialize(1);
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@ -414,9 +414,9 @@ int stm32_spidev_bus_init(void)
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return -ENODEV;
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return -ENODEV;
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}
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}
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/* Default SPI1 to NUCLEO_SPI2_FREQ and mode */
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/* Default SPI2 to NUCLEO_SPI2_FREQ and mode */
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SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI1_TEST_FREQ);
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SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ);
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SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS);
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SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS);
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SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE);
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SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE);
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SPI_EXCHANGE(spi2, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
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SPI_EXCHANGE(spi2, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
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@ -431,13 +431,15 @@ int stm32_spidev_bus_init(void)
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return -ENODEV;
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return -ENODEV;
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}
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}
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/* Default SPI1 to NUCLEO_SPI3_FREQ and mode */
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/* Default SPI3 to NUCLEO_SPI3_FREQ and mode */
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SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ);
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SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ);
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SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS);
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SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS);
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SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE);
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SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE);
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SPI_EXCHANGE(spi3, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
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SPI_EXCHANGE(spi3, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
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#endif
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#endif
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return OK;
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}
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}
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#endif /* NUCLEO_SPI_TEST */
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#endif /* NUCLEO_SPI_TEST */
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#endif /* defined(CONFIG_SPI) */
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#endif /* defined(CONFIG_SPI) */
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