configs/nucleo-144: Test F7 SPI

This commit is contained in:
David Sidrane 2016-06-14 07:30:28 -06:00 committed by Gregory Nutt
parent ccfcb12ef7
commit 4f72ad74d2
6 changed files with 85 additions and 20 deletions

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@ -21,6 +21,7 @@ Contents
- U[S]ARTs and Serial Consoles
- SPI
- SDIO - MMC
- SPI Test
- Configurations
f7xx-nsh
f7xx-evalos
@ -437,6 +438,40 @@ SDIO
DAT2 PC10 CN11-1
CD PC11 CN11-2
SPI Test
========
The builtin SPI test facility can be enabled with the following settings:
+CONFIG_STM32F7_SPI=y
+CONFIG_STM32F7_SPI1=y
+CONFIG_STM32F7_SPI2=y
+CONFIG_STM32F7_SPI3=y
+# CONFIG_STM32F7_SPI_INTERRUPTS is not set
+# CONFIG_STM32F7_SPI_DMA is not set
# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
+CONFIG_NUCLEO_SPI_TEST=y
+CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World"
+CONFIG_NUCLEO_SPI1_TEST=y
+CONFIG_NUCLEO_SPI1_TEST_FREQ=1000000
+CONFIG_NUCLEO_SPI1_TEST_BITS=8
+CONFIG_NUCLEO_SPI1_TEST_MODE3=y
+CONFIG_NUCLEO_SPI2_TEST=y
+CONFIG_NUCLEO_SPI2_TEST_FREQ=12000000
+CONFIG_NUCLEO_SPI2_TEST_BITS=8
+CONFIG_NUCLEO_SPI2_TEST_MODE3=y
+CONFIG_NUCLEO_SPI3_TEST=y
+CONFIG_NUCLEO_SPI3_TEST_FREQ=40000000
+CONFIG_NUCLEO_SPI3_TEST_BITS=8
+CONFIG_NUCLEO_SPI3_TEST_MODE3=y
+CONFIG_LIB_BOARDCTL=y
+CONFIG_NSH_ARCHINIT=y
Configurations
==============

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@ -296,6 +296,7 @@
/* USART3:
* Use USART3 and the USB virtual COM port
*/
#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
# define GPIO_USART3_RX GPIO_USART3_RX_3
# define GPIO_USART3_TX GPIO_USART3_TX_3
@ -307,9 +308,36 @@
* with the serial interface with the adaptor's RX on pin CN11 pin 64 and
* TX on pin CN11 pin 61
*
* USART8: has noit remap
* USART8: has no remap
*/
/* SPI
*
*
* PA6 MISO CN12-13
* PA7 MOSI CN12-15
* PA5 SCK CN12-11
*
* PB14 MISO CN12-28
* PB15 MOSI CN12-26
* PB10 SCK CN12-25
*
* PB4 MISO CN12-27
* PB5 MOSI CN12-29
* PB3 SCK CN12-31
*/
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
*

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@ -102,11 +102,11 @@
GPIO_OUTPUT_SET)
#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13)
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13)
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
@ -164,7 +164,7 @@ void stm32_spidev_initialize(void);
*
************************************************************************************/
#if defined(NUCLEO_SPI_TEST)
#if defined(CONFIG_NUCLEO_SPI_TEST)
int stm32_spidev_bus_test(void);
#endif

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@ -111,10 +111,10 @@ int board_app_initialize(uintptr_t arg)
#if defined(CONFIG_NUCLEO_SPI_TEST)
/* Create SPI interfaces */
ret = stm32_spidev_bus_init();
ret = stm32_spidev_bus_test();
if (ret != OK)
{
ferr("ERROR: Failed to initialize SPI interfaces: %d\n", ret);
syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", ret);
return ret;
}
#endif

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@ -70,7 +70,7 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#if defined(CONFIG__SPI)
#if defined(CONFIG_SPI)
/* Configure SPI chip selects */
stm32_spidev_initialize();

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@ -228,7 +228,7 @@ void weak_function stm32_spidev_initialize(void)
void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(g_spigpio[i], !selected);
stm32_gpiowrite(g_spigpio[devid], !selected);
}
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -241,7 +241,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(g_spigpio[i], !selected);
stm32_gpiowrite(g_spigpio[devid], !selected);
}
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -254,7 +254,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(g_spigpio[i], !selected);
stm32_gpiowrite(g_spigpio[devid], !selected);
}
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -271,7 +271,7 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(g_spigpio[i], !selected);
stm32_gpiowrite(g_spigpio[devid], !selected);
}
uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -288,7 +288,7 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(g_spigpio[i], !selected);
stm32_gpiowrite(g_spigpio[devid], !selected);
}
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -304,7 +304,7 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(g_spigpio[i], !selected);
stm32_gpiowrite(g_spigpio[devid], !selected);
}
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -382,11 +382,11 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
#endif /* CONFIG_SPI_CMDDATA */
#if defined(CONFIG_NUCLEO_SPI_TEST)
int stm32_spidev_bus_init(void)
int stm32_spidev_bus_test(void)
{
/* Configure and test SPI-*/
uint8_t *tx = CONFIG_NUCLEO_SPI_TEST_MESSAGE;
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE;
#if defined(CONFIG_NUCLEO_SPI1_TEST)
spi1 = stm32_spibus_initialize(1);
@ -414,9 +414,9 @@ int stm32_spidev_bus_init(void)
return -ENODEV;
}
/* Default SPI1 to NUCLEO_SPI2_FREQ and mode */
/* Default SPI2 to NUCLEO_SPI2_FREQ and mode */
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI1_TEST_FREQ);
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ);
SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS);
SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE);
SPI_EXCHANGE(spi2, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
@ -431,13 +431,15 @@ int stm32_spidev_bus_init(void)
return -ENODEV;
}
/* Default SPI1 to NUCLEO_SPI3_FREQ and mode */
/* Default SPI3 to NUCLEO_SPI3_FREQ and mode */
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ);
SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS);
SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE);
SPI_EXCHANGE(spi3, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
#endif
return OK;
}
#endif /* NUCLEO_SPI_TEST */
#endif /* defined(CONFIG_SPI) */