SAMA5 boards: Add set up for 528MHz CPU clock
This commit is contained in:
Gregory Nutt
parent
2a1a468fe1
commit
52cfdccd7a
@ -5,6 +5,21 @@
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if ARCH_BOARD_SAMA5D3_XPLAINED
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choice
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prompt "CPU Frequency"
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default SAMA5D3XPLAINED_396MHZ
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config SAMA5D3XPLAINED_384MHZ
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bool "384 MHz"
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config SAMA5D3XPLAINED_396MHZ
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bool "396 MHz"
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config SAMA5D3XPLAINED_528MHZ
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bool "528 MHz"
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endchoice # CPU Frequency
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choice
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prompt "SAMA5D3-Xplained DRAM Type"
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default SAMA5D3XPLAINED_MT47H128M16RT
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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@ -63,7 +63,26 @@
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# include <arch/board/board_sdram.h>
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#elif 1 /* #elif !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */
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#elif defined(CONFIG_SAMA5D3XPLAINED_384MHZ)
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/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz
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* USB clock with the required accuracy using only PLLA. When PPLA is used to clock
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* OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup
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* results in a CPU clock of 384MHz.
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*
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* This case is only interesting for experimentation.
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*/
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# include <arch/board/board_384mhz.h>
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#elif defined(CONFIG_SAMA5D3XPLAINED_528MHZ)
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/* This is the configuration results in a CPU clock of 528MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_529mhz.h>
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#else /* #elif defined(CONFIG_SAMA5D3XPLAINED_396MHZ) */
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/* This is the configuration provided in the Atmel example code. This setup results
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* in a CPU clock of 396MHz.
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*
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@ -72,15 +91,6 @@
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# include <arch/board/board_396mhz.h>
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#else
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/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz
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* USB clock with the required accuracy using only PLLA. When PPLA is used to clock
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* OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup
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* results in a CPU clock of 384MHz.
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*/
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# include <arch/board/board_384mhz.h>
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#endif
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/* LED definitions ******************************************************************/
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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@ -190,19 +190,6 @@
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* FLASH wait states
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*
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* FWS Max frequency
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* 1.62V 1.8V
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* --- ----- ------
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* 0 24MHz 27MHz
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* 1 40MHz 47MHz
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* 2 72MHz 84MHz
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* 3 84MHz 96MHz
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*/
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#define BOARD_FWS 3
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/************************************************************************************
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* Public Data
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************************************************************************************/
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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@ -181,19 +181,6 @@
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* FLASH wait states
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*
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* FWS Max frequency
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* 1.62V 1.8V
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* --- ----- ------
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* 0 24MHz 27MHz
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* 1 40MHz 47MHz
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* 2 72MHz 84MHz
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* 3 84MHz 96MHz
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*/
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#define BOARD_FWS 3
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/************************************************************************************
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* Public Data
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************************************************************************************/
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207
configs/sama5d3-xplained/include/board_528mhz.h
Normal file
207
configs/sama5d3-xplained/include/board_528mhz.h
Normal file
@ -0,0 +1,207 @@
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/************************************************************************************
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* configs/sama5d3-xplained/include/board_528mhz.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_528MHZ_H
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#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_528MHZ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These
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* definitions will configure operational clocking.
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*
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* This is the configuration results in a CPU clock of 528MHz:
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*
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* MAINOSC: Frequency = 12MHz (crystal)
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* PLLA: PLL Divider = 1, Multiplier = 43+1 to generate PLLACK = 528MHz
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* Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate
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* MCK = 132MHz
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* CPU clock = 528MHz
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*/
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/* Main oscillator register settings.
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*
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* The start up time should be should be:
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multipler = 43+1
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*/
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_OUT (0)
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#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings.
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*
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* Master/Processor Clock Source Selection = PLLA
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* Master/Processor Clock Prescaler = 1
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* PLLA Divider = 1
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* Master Clock Division (MDIV) = 4
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*
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* NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
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*
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* Prescaler input = 528MHz / 1 = 528MHz
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* Prescaler output = 528MHz / 1 = 528MHz
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* Processor Clock (PCK) = 528MHz
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* Master clock (MCK) = 528MHz / 4 = 132MHz
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
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#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV1
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#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV4
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/* ADC Configuration
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*
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* ADCClock = MCK / ((PRESCAL+1) * 2)
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*
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* Given:
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* MCK = 132MHz
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* ADCClock = 8MHz
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* Then:
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* PRESCAL = 7.25
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*
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* PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz
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*/
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
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/* Resulting frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_PLLA_FREQUENCY (528000000) /* PLLACK: 44 * 12Mhz / 1 */
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#define BOARD_PCK_FREQUENCY (528000000) /* CPU: PLLACK / 1 / 1 */
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
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* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
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* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
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* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
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* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
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*
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* For High-speed operations, the user has to perform the following:
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*
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
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* PMC_PCER register.
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* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
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* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
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* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
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* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
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* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
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* register.
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* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
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* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
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* selected.
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* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
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*
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* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
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* driver is initialized.
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*/
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# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
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# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
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# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
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#endif
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */
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#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
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/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_528MHZ_H */
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@ -5,6 +5,21 @@
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if ARCH_BOARD_SAMA5D3X_EK
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choice
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prompt "CPU Frequency"
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default SAMA5D3xEK_396MHZ
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config SAMA5D3xEK_384MHZ
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bool "384 MHz"
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config SAMA5D3xEK_396MHZ
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bool "396 MHz"
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config SAMA5D3xEK_528MHZ
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bool "528 MHz"
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endchoice # CPU Frequency
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choice
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prompt "SAMA5D3x-EK DRAM Type"
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default SAMA5D3xEK_MT47H128M16RT
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@ -1,7 +1,7 @@
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/************************************************************************************
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* configs/sama5d3x-ek/include/board.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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@ -63,7 +63,26 @@
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# include <arch/board/board_sdram.h>
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#elif 1 /* #elif !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */
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#elif defined(CONFIG_SAMA5D3xEK_384MHZ)
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/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz
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* USB clock with the required accuracy using only PLLA. When PPLA is used to clock
|
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* OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup
|
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* results in a CPU clock of 384MHz.
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*
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* This case is only interesting for experimentation.
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*/
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# include <arch/board/board_384mhz.h>
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#elif defined(CONFIG_SAMA5D3xEK_528MHZ)
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/* This is the configuration results in a CPU clock of 528MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_529mhz.h>
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#else /* #elif defined(CONFIG_SAMA5D3xEK_396MHZ) */
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/* This is the configuration provided in the Atmel example code. This setup results
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* in a CPU clock of 396MHz.
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*
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@ -72,15 +91,6 @@
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# include <arch/board/board_396mhz.h>
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#else
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/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz
|
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* USB clock with the required accuracy using only PLLA. When PPLA is used to clock
|
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* OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup
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* results in a CPU clock of 384MHz.
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*/
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# include <arch/board/board_384mhz.h>
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#endif
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/* LCD Interface, Geometry and Timing */
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@ -1,7 +1,7 @@
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/************************************************************************************
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* configs/sama5d3x-ek/include/board_384mhz.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
|
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
|
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************************************************************************************/
|
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/* Clocking *************************************************************************/
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@ -190,19 +190,6 @@
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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|
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/* FLASH wait states
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*
|
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* FWS Max frequency
|
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* 1.62V 1.8V
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* --- ----- ------
|
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* 0 24MHz 27MHz
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* 1 40MHz 47MHz
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* 2 72MHz 84MHz
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* 3 84MHz 96MHz
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*/
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#define BOARD_FWS 3
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* configs/sama5d3x-ek/include/board_396mhz.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
@ -181,19 +181,6 @@
|
||||
#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
|
||||
#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
* FWS Max frequency
|
||||
* 1.62V 1.8V
|
||||
* --- ----- ------
|
||||
* 0 24MHz 27MHz
|
||||
* 1 40MHz 47MHz
|
||||
* 2 72MHz 84MHz
|
||||
* 3 84MHz 96MHz
|
||||
*/
|
||||
|
||||
#define BOARD_FWS 3
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
207
configs/sama5d3x-ek/include/board_528mhz.h
Normal file
207
configs/sama5d3x-ek/include/board_528mhz.h
Normal file
@ -0,0 +1,207 @@
|
||||
/************************************************************************************
|
||||
* configs/sama5d3x-ek/include/board_528mhz.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_528MHZ_H
|
||||
#define __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_528MHZ_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These
|
||||
* definitions will configure operational clocking.
|
||||
*
|
||||
* This is the configuration results in a CPU clock of 528MHz:
|
||||
*
|
||||
* MAINOSC: Frequency = 12MHz (crystal)
|
||||
* PLLA: PLL Divider = 1, Multiplier = 43+1 to generate PLLACK = 528MHz
|
||||
* Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate
|
||||
* MCK = 132MHz
|
||||
* CPU clock = 528MHz
|
||||
*/
|
||||
|
||||
/* Main oscillator register settings.
|
||||
*
|
||||
* The start up time should be should be:
|
||||
* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
|
||||
*/
|
||||
|
||||
#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
|
||||
|
||||
/* PLLA configuration.
|
||||
*
|
||||
* Divider = 1
|
||||
* Multipler = 43+1
|
||||
*/
|
||||
|
||||
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
|
||||
#define BOARD_CKGR_PLLAR_OUT (0)
|
||||
#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT)
|
||||
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
|
||||
|
||||
/* PMC master clock register settings.
|
||||
*
|
||||
* Master/Processor Clock Source Selection = PLLA
|
||||
* Master/Processor Clock Prescaler = 1
|
||||
* PLLA Divider = 1
|
||||
* Master Clock Division (MDIV) = 4
|
||||
*
|
||||
* NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
|
||||
*
|
||||
* Prescaler input = 528MHz / 1 = 528MHz
|
||||
* Prescaler output = 528MHz / 1 = 528MHz
|
||||
* Processor Clock (PCK) = 528MHz
|
||||
* Master clock (MCK) = 528MHz / 4 = 132MHz
|
||||
*/
|
||||
|
||||
#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
|
||||
#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
|
||||
#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV1
|
||||
#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV4
|
||||
|
||||
/* ADC Configuration
|
||||
*
|
||||
* ADCClock = MCK / ((PRESCAL+1) * 2)
|
||||
*
|
||||
* Given:
|
||||
* MCK = 132MHz
|
||||
* ADCClock = 8MHz
|
||||
* Then:
|
||||
* PRESCAL = 7.25
|
||||
*
|
||||
* PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz
|
||||
*/
|
||||
|
||||
#define BOARD_ADC_PRESCAL (7)
|
||||
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
|
||||
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
|
||||
#define BOARD_PLLA_FREQUENCY (528000000) /* PLLACK: 44 * 12Mhz / 1 */
|
||||
#define BOARD_PCK_FREQUENCY (528000000) /* CPU: PLLACK / 1 / 1 */
|
||||
#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */
|
||||
#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
|
||||
|
||||
#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
|
||||
defined(CONFIG_SAMA5_UDPHS)
|
||||
|
||||
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
|
||||
* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
|
||||
* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
|
||||
* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
|
||||
* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
|
||||
*
|
||||
* For High-speed operations, the user has to perform the following:
|
||||
*
|
||||
* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
|
||||
* PMC_PCER register.
|
||||
* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
|
||||
* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
|
||||
* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
|
||||
* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
|
||||
* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
|
||||
* register.
|
||||
* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
|
||||
* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
|
||||
* selected.
|
||||
* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
|
||||
*
|
||||
* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
|
||||
* driver is initialized.
|
||||
*/
|
||||
|
||||
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
|
||||
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
|
||||
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
|
||||
#endif
|
||||
|
||||
/* HSMCI clocking
|
||||
*
|
||||
* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
|
||||
* divided by (2*(CLKDIV) + CLOCKODD + 2).
|
||||
*
|
||||
* MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
|
||||
*
|
||||
* Where CLKDIV has a range of 0-255.
|
||||
*/
|
||||
|
||||
/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */
|
||||
|
||||
#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT)
|
||||
|
||||
/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */
|
||||
|
||||
#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
|
||||
|
||||
/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */
|
||||
|
||||
#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
|
||||
#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_528MHZ_H */
|
||||
Loading…
Reference in New Issue
Block a user